clksrc            409 arch/arm/mach-omap2/timer.c static struct omap_dm_timer clksrc;
clksrc            417 arch/arm/mach-omap2/timer.c 	return (u64)__omap_dm_timer_read_counter(&clksrc,
clksrc            430 arch/arm/mach-omap2/timer.c 	if (clksrc.reserved)
clksrc            431 arch/arm/mach-omap2/timer.c 		return __omap_dm_timer_read_counter(&clksrc,
clksrc            488 arch/arm/mach-omap2/timer.c 		__omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
clksrc            497 arch/arm/mach-omap2/timer.c 	__omap_dm_timer_load_start(&clksrc,
clksrc            509 arch/arm/mach-omap2/timer.c 	clksrc.id = gptimer_id;
clksrc            510 arch/arm/mach-omap2/timer.c 	clksrc.errata = omap_dm_timer_get_errata();
clksrc            512 arch/arm/mach-omap2/timer.c 	res = omap_dm_timer_init_one(&clksrc, fck_source, property,
clksrc            526 arch/arm/mach-omap2/timer.c 	__omap_dm_timer_load_start(&clksrc,
clksrc            529 arch/arm/mach-omap2/timer.c 	sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
clksrc            531 arch/arm/mach-omap2/timer.c 	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
clksrc            536 arch/arm/mach-omap2/timer.c 			clocksource_gpt.name, clksrc.rate);
clksrc            219 arch/m68k/atari/debug.c 	int clksrc, clkmode, div, reg3, reg5;
clksrc            227 arch/m68k/atari/debug.c 	clksrc  = clksrc_table[baud];
clksrc            232 arch/m68k/atari/debug.c 		clksrc = 0x28;		/* TRxC */
clksrc            252 arch/m68k/atari/debug.c 	SCC_WRITE(11, clksrc);		/* main clock source */
clksrc             12 drivers/clocksource/mmio.c 	struct clocksource clksrc;
clksrc             17 drivers/clocksource/mmio.c 	return container_of(c, struct clocksource_mmio, clksrc);
clksrc             63 drivers/clocksource/mmio.c 	cs->clksrc.name = name;
clksrc             64 drivers/clocksource/mmio.c 	cs->clksrc.rating = rating;
clksrc             65 drivers/clocksource/mmio.c 	cs->clksrc.read = read;
clksrc             66 drivers/clocksource/mmio.c 	cs->clksrc.mask = CLOCKSOURCE_MASK(bits);
clksrc             67 drivers/clocksource/mmio.c 	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
clksrc             69 drivers/clocksource/mmio.c 	return clocksource_register_hz(&cs->clksrc, hz);
clksrc             40 drivers/clocksource/timer-atmel-pit.c 	struct clocksource		clksrc;
clksrc             49 drivers/clocksource/timer-atmel-pit.c static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
clksrc             51 drivers/clocksource/timer-atmel-pit.c 	return container_of(clksrc, struct pit_data, clksrc);
clksrc            221 drivers/clocksource/timer-atmel-pit.c 	data->clksrc.mask = CLOCKSOURCE_MASK(bits);
clksrc            222 drivers/clocksource/timer-atmel-pit.c 	data->clksrc.name = "pit";
clksrc            223 drivers/clocksource/timer-atmel-pit.c 	data->clksrc.rating = 175;
clksrc            224 drivers/clocksource/timer-atmel-pit.c 	data->clksrc.read = read_pit_clk;
clksrc            225 drivers/clocksource/timer-atmel-pit.c 	data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
clksrc            227 drivers/clocksource/timer-atmel-pit.c 	ret = clocksource_register_hz(&data->clksrc, pit_rate);
clksrc            239 drivers/clocksource/timer-atmel-pit.c 		clocksource_unregister(&data->clksrc);
clksrc            110 drivers/clocksource/timer-atmel-tcb.c static struct clocksource clksrc = {
clksrc            121 drivers/clocksource/timer-atmel-tcb.c 	return tc_get_cycles(&clksrc);
clksrc            126 drivers/clocksource/timer-atmel-tcb.c 	return tc_get_cycles32(&clksrc);
clksrc            133 drivers/clocksource/timer-atmel-tcb.c 	return tc_get_cycles(&clksrc);
clksrc            138 drivers/clocksource/timer-atmel-tcb.c 	return tc_get_cycles32(&clksrc);
clksrc            435 drivers/clocksource/timer-atmel-tcb.c 	clksrc.name = kbasename(node->parent->full_name);
clksrc            437 drivers/clocksource/timer-atmel-tcb.c 	pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
clksrc            444 drivers/clocksource/timer-atmel-tcb.c 		clksrc.read = tc_get_cycles32;
clksrc            465 drivers/clocksource/timer-atmel-tcb.c 	ret = clocksource_register_hz(&clksrc, divided_rate);
clksrc            482 drivers/clocksource/timer-atmel-tcb.c 	clocksource_unregister(&clksrc);
clksrc             80 drivers/clocksource/timer-nps.c static u64 nps_clksrc_read(struct clocksource *clksrc)
clksrc             53 drivers/clocksource/timer-sun5i.c 	struct clocksource	clksrc;
clksrc             57 drivers/clocksource/timer-sun5i.c 	container_of(x, struct sun5i_timer_clksrc, clksrc)
clksrc            156 drivers/clocksource/timer-sun5i.c static u64 sun5i_clksrc_read(struct clocksource *clksrc)
clksrc            158 drivers/clocksource/timer-sun5i.c 	struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
clksrc            172 drivers/clocksource/timer-sun5i.c 		clocksource_unregister(&cs->clksrc);
clksrc            176 drivers/clocksource/timer-sun5i.c 		clocksource_register_hz(&cs->clksrc, ndata->new_rate);
clksrc            226 drivers/clocksource/timer-sun5i.c 	cs->clksrc.name = node->name;
clksrc            227 drivers/clocksource/timer-sun5i.c 	cs->clksrc.rating = 340;
clksrc            228 drivers/clocksource/timer-sun5i.c 	cs->clksrc.read = sun5i_clksrc_read;
clksrc            229 drivers/clocksource/timer-sun5i.c 	cs->clksrc.mask = CLOCKSOURCE_MASK(32);
clksrc            230 drivers/clocksource/timer-sun5i.c 	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
clksrc            232 drivers/clocksource/timer-sun5i.c 	ret = clocksource_register_hz(&cs->clksrc, rate);
clksrc             69 drivers/gpu/drm/shmobile/shmob_drm_drv.c 					    enum shmob_drm_clk_source clksrc)
clksrc             74 drivers/gpu/drm/shmobile/shmob_drm_drv.c 	switch (clksrc) {
clksrc            509 drivers/mfd/sm501.c 			      int clksrc,
clksrc            526 drivers/mfd/sm501.c 	switch (clksrc) {
clksrc            590 drivers/mfd/sm501.c 	clock = clock & ~(0xFF << clksrc);
clksrc            591 drivers/mfd/sm501.c 	clock |= reg<<clksrc;
clksrc            640 drivers/mfd/sm501.c 			       int clksrc,
clksrc            647 drivers/mfd/sm501.c 	switch (clksrc) {
clksrc            179 drivers/mmc/host/sdhci-s3c.c 	struct clk *clksrc = ourhost->clk_bus[src];
clksrc            182 drivers/mmc/host/sdhci-s3c.c 	if (IS_ERR(clksrc))
clksrc            190 drivers/mmc/host/sdhci-s3c.c 		rate = clk_round_rate(clksrc, wanted);
clksrc             38 drivers/net/dsa/sja1105/sja1105_clocking.c 	u64 clksrc;
clksrc             85 drivers/net/dsa/sja1105/sja1105_clocking.c 	u64 clksrc;
clksrc             95 drivers/net/dsa/sja1105/sja1105_clocking.c 	sja1105_packing(buf, &idiv->clksrc,    28, 24, size, op);
clksrc            115 drivers/net/dsa/sja1105/sja1105_clocking.c 	idiv.clksrc    = 0x0A;            /* 25MHz */
clksrc            132 drivers/net/dsa/sja1105/sja1105_clocking.c 	sja1105_packing(buf, &cmd->clksrc,    28, 24, size, op);
clksrc            157 drivers/net/dsa/sja1105/sja1105_clocking.c 	int clksrc;
clksrc            160 drivers/net/dsa/sja1105/sja1105_clocking.c 		clksrc = mac_clk_sources[port];
clksrc            162 drivers/net/dsa/sja1105/sja1105_clocking.c 		clksrc = phy_clk_sources[port];
clksrc            165 drivers/net/dsa/sja1105/sja1105_clocking.c 	mii_tx_clk.clksrc    = clksrc;
clksrc            190 drivers/net/dsa/sja1105/sja1105_clocking.c 	mii_rx_clk.clksrc    = clk_sources[port];
clksrc            215 drivers/net/dsa/sja1105/sja1105_clocking.c 	mii_ext_tx_clk.clksrc    = clk_sources[port];
clksrc            240 drivers/net/dsa/sja1105/sja1105_clocking.c 	mii_ext_rx_clk.clksrc    = clk_sources[port];
clksrc            322 drivers/net/dsa/sja1105/sja1105_clocking.c 	int clksrc;
clksrc            325 drivers/net/dsa/sja1105/sja1105_clocking.c 		clksrc = CLKSRC_PLL0;
clksrc            329 drivers/net/dsa/sja1105/sja1105_clocking.c 		clksrc = clk_sources[port];
clksrc            333 drivers/net/dsa/sja1105/sja1105_clocking.c 	txc.clksrc = clksrc;
clksrc            545 drivers/net/dsa/sja1105/sja1105_clocking.c 	ref_clk.clksrc    = clk_sources[port];
clksrc            563 drivers/net/dsa/sja1105/sja1105_clocking.c 	ext_tx_clk.clksrc    = CLKSRC_PLL1;
clksrc            384 drivers/net/dsa/sja1105/sja1105_static_config.c 	sja1105_packing(buf, &entry->clksrc,    31, 30, size, op);
clksrc            155 drivers/net/dsa/sja1105/sja1105_static_config.h 	u64 clksrc;
clksrc            187 drivers/net/dsa/sja1105/sja1105_tas.c 	schedule_entry_points_params->clksrc = SJA1105_TAS_CLKSRC_STANDALONE;
clksrc            292 drivers/spi/spi-rspi.c 	unsigned long clksrc;
clksrc            297 drivers/spi/spi-rspi.c 	clksrc = clk_get_rate(rspi->clk);
clksrc            299 drivers/spi/spi-rspi.c 		if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
clksrc            302 drivers/spi/spi-rspi.c 		clksrc /= 2;
clksrc            306 drivers/spi/spi-rspi.c 	spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
clksrc            558 drivers/tty/serial/max310x.c 	unsigned int div, clksrc, pllcfg = 0;
clksrc            600 drivers/tty/serial/max310x.c 	clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
clksrc            604 drivers/tty/serial/max310x.c 		clksrc |= MAX310X_CLKSRC_PLL_BIT;
clksrc            607 drivers/tty/serial/max310x.c 		clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
clksrc            609 drivers/tty/serial/max310x.c 	regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
clksrc             13 include/linux/sm501.h 				     int clksrc, unsigned long freq);
clksrc             16 include/linux/sm501.h 				      int clksrc, unsigned long req_freq);
clksrc            716 sound/soc/codecs/cs35l35.c 	int clksrc;
clksrc            721 sound/soc/codecs/cs35l35.c 		clksrc = CS35L35_CLK_SOURCE_MCLK;
clksrc            724 sound/soc/codecs/cs35l35.c 		clksrc = CS35L35_CLK_SOURCE_SCLK;
clksrc            727 sound/soc/codecs/cs35l35.c 		clksrc = CS35L35_CLK_SOURCE_PDM;
clksrc            754 sound/soc/codecs/cs35l35.c 				clksrc << CS35L35_CLK_SOURCE_SHIFT);
clksrc             54 sound/soc/codecs/cs35l36.c 	int clksrc;
clksrc           1012 sound/soc/codecs/cs35l36.c 	prev_clksrc = cs35l36->clksrc;
clksrc           1016 sound/soc/codecs/cs35l36.c 		cs35l36->clksrc = CS35L36_PLLSRC_SCLK;
clksrc           1019 sound/soc/codecs/cs35l36.c 		cs35l36->clksrc = CS35L36_PLLSRC_LRCLK;
clksrc           1022 sound/soc/codecs/cs35l36.c 		cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK;
clksrc           1025 sound/soc/codecs/cs35l36.c 		cs35l36->clksrc = CS35L36_PLLSRC_SELF;
clksrc           1028 sound/soc/codecs/cs35l36.c 		cs35l36->clksrc = CS35L36_PLLSRC_MCLK;
clksrc           1051 sound/soc/codecs/cs35l36.c 			   cs35l36->clksrc);
clksrc           1082 sound/soc/codecs/cs35l36.c 	if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) {
clksrc            237 sound/soc/fsl/fsl_esai.c 	struct clk *clksrc = esai_priv->extalclk;
clksrc            267 sound/soc/fsl/fsl_esai.c 		clksrc = esai_priv->fsysclk;
clksrc            279 sound/soc/fsl/fsl_esai.c 	if (IS_ERR(clksrc)) {
clksrc            282 sound/soc/fsl/fsl_esai.c 		return PTR_ERR(clksrc);
clksrc            284 sound/soc/fsl/fsl_esai.c 	clk_rate = clk_get_rate(clksrc);
clksrc            302 sound/soc/fsl/fsl_esai.c 	if (ratio == 1 && clksrc == esai_priv->extalclk) {
clksrc            357 sound/soc/fsl/fsl_spdif.c 	u8 clksrc = spdif_priv->rxclk_src;
clksrc            359 sound/soc/fsl/fsl_spdif.c 	if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
clksrc            364 sound/soc/fsl/fsl_spdif.c 			SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
clksrc            823 sound/soc/fsl/fsl_spdif.c 	u8 clksrc;
clksrc            828 sound/soc/fsl/fsl_spdif.c 	clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
clksrc            831 sound/soc/fsl/fsl_spdif.c 	if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))