clkreg 148 drivers/ata/pata_ftide010.c u8 clkreg; clkreg 161 drivers/ata/pata_ftide010.c clkreg = readb(ftide->base + FTIDE010_CLK_MOD); clkreg 162 drivers/ata/pata_ftide010.c clkreg &= ~udma_en_mask; clkreg 163 drivers/ata/pata_ftide010.c clkreg &= ~f66m_en_mask; clkreg 170 drivers/ata/pata_ftide010.c clkreg |= udma_en_mask; clkreg 172 drivers/ata/pata_ftide010.c clkreg |= f66m_en_mask; clkreg 185 drivers/ata/pata_ftide010.c clkreg, timreg); clkreg 187 drivers/ata/pata_ftide010.c writeb(clkreg, ftide->base + FTIDE010_CLK_MOD); clkreg 195 drivers/ata/pata_ftide010.c clkreg |= f66m_en_mask; clkreg 204 drivers/ata/pata_ftide010.c clkreg, timreg); clkreg 206 drivers/ata/pata_ftide010.c writeb(clkreg, ftide->base + FTIDE010_CLK_MOD); clkreg 135 drivers/mmc/host/mmci.c .clkreg = MCI_CLK_ENABLE, clkreg 161 drivers/mmc/host/mmci.c .clkreg = MCI_CLK_ENABLE, clkreg 193 drivers/mmc/host/mmci.c .clkreg = MCI_CLK_ENABLE, clkreg 226 drivers/mmc/host/mmci.c .clkreg = MCI_CLK_ENABLE, clkreg 270 drivers/mmc/host/mmci.c .clkreg = MCI_CLK_ENABLE, clkreg 366 drivers/mmc/host/mmci.c u32 clk = variant->clkreg; clkreg 310 drivers/mmc/host/mmci.h unsigned int clkreg; clkreg 7990 drivers/net/ethernet/broadcom/bnx2.c u32 clkreg; clkreg 7994 drivers/net/ethernet/broadcom/bnx2.c clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); clkreg 7996 drivers/net/ethernet/broadcom/bnx2.c clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; clkreg 7997 drivers/net/ethernet/broadcom/bnx2.c switch (clkreg) {