clk_src_count     323 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < pool->clk_src_count; i++) {
clk_src_count    2487 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < pool->clk_src_count; ++i) {
clk_src_count     725 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     934 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		pool->base.clk_src_count = 3;
clk_src_count     944 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		pool->base.clk_src_count = 2;
clk_src_count     953 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1476 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->clk_src_count; i++) {
clk_src_count     782 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1314 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		pool->base.clk_src_count = 2;
clk_src_count    1325 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     744 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1202 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
clk_src_count    1209 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     600 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1040 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
clk_src_count    1047 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     773 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     915 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.clk_src_count = 3;
clk_src_count     925 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.clk_src_count = 2;
clk_src_count     934 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1112 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.clk_src_count = 3;
clk_src_count    1122 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.clk_src_count = 2;
clk_src_count    1131 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1307 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.clk_src_count = 2;
clk_src_count    1315 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		pool->base.clk_src_count = 1;
clk_src_count    1324 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     949 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
clk_src_count    1346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
clk_src_count    1354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    3517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
clk_src_count    3524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     916 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count    1502 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
clk_src_count    1510 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.clk_src_count; i++) {
clk_src_count     216 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	unsigned int clk_src_count;