clk_rst_ctl        33 arch/mips/cavium-octeon/octeon-platform.c 	union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
clk_rst_ctl        39 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
clk_rst_ctl        40 arch/mips/cavium-octeon/octeon-platform.c 	if (clk_rst_ctl.s.hrst) {
clk_rst_ctl        60 arch/mips/cavium-octeon/octeon-platform.c 	union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
clk_rst_ctl       120 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
clk_rst_ctl       126 arch/mips/cavium-octeon/octeon-platform.c 	if (clk_rst_ctl.s.hrst)
clk_rst_ctl       129 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.p_por = 1;
clk_rst_ctl       130 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.hrst = 0;
clk_rst_ctl       131 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.p_prst = 0;
clk_rst_ctl       132 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.h_clkdiv_rst = 0;
clk_rst_ctl       133 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.o_clkdiv_rst = 0;
clk_rst_ctl       134 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.h_clkdiv_en = 0;
clk_rst_ctl       135 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.o_clkdiv_en = 0;
clk_rst_ctl       136 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       139 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
clk_rst_ctl       146 arch/mips/cavium-octeon/octeon-platform.c 		clk_rst_ctl.s.p_refclk_div = 0;
clk_rst_ctl       149 arch/mips/cavium-octeon/octeon-platform.c 		clk_rst_ctl.s.p_refclk_div = 1;
clk_rst_ctl       152 arch/mips/cavium-octeon/octeon-platform.c 		clk_rst_ctl.s.p_refclk_div = 2;
clk_rst_ctl       155 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       186 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.h_div = div;
clk_rst_ctl       187 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       189 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
clk_rst_ctl       190 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.h_clkdiv_en = 1;
clk_rst_ctl       191 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       193 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.h_clkdiv_rst = 1;
clk_rst_ctl       194 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       203 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.p_por = 0;
clk_rst_ctl       204 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       213 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.o_clkdiv_rst = 1;
clk_rst_ctl       214 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       217 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.o_clkdiv_en = 1;
clk_rst_ctl       218 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       227 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.p_prst = 1;
clk_rst_ctl       228 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       234 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.p_prst = 0;
clk_rst_ctl       235 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       241 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.p_prst = 1;
clk_rst_ctl       242 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
clk_rst_ctl       248 arch/mips/cavium-octeon/octeon-platform.c 	clk_rst_ctl.s.hrst = 1;
clk_rst_ctl       249 arch/mips/cavium-octeon/octeon-platform.c 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);