clk_rst 51 arch/arm/mach-mmp/clock-mmp2.c uint32_t clk_rst; clk_rst 53 arch/arm/mach-mmp/clock-mmp2.c clk_rst = __raw_readl(clk->clk_rst); clk_rst 54 arch/arm/mach-mmp/clock-mmp2.c clk_rst |= clk->enable_val; clk_rst 55 arch/arm/mach-mmp/clock-mmp2.c __raw_writel(clk_rst, clk->clk_rst); clk_rst 60 arch/arm/mach-mmp/clock-mmp2.c uint32_t clk_rst; clk_rst 62 arch/arm/mach-mmp/clock-mmp2.c clk_rst = __raw_readl(clk->clk_rst); clk_rst 63 arch/arm/mach-mmp/clock-mmp2.c clk_rst &= ~clk->enable_val; clk_rst 64 arch/arm/mach-mmp/clock-mmp2.c __raw_writel(clk_rst, clk->clk_rst); clk_rst 18 arch/arm/mach-mmp/clock.c uint32_t clk_rst; clk_rst 20 arch/arm/mach-mmp/clock.c clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); clk_rst 21 arch/arm/mach-mmp/clock.c __raw_writel(clk_rst, clk->clk_rst); clk_rst 26 arch/arm/mach-mmp/clock.c __raw_writel(0, clk->clk_rst); clk_rst 36 arch/arm/mach-mmp/clock.c __raw_writel(clk->enable_val, clk->clk_rst); clk_rst 41 arch/arm/mach-mmp/clock.c __raw_writel(0, clk->clk_rst); clk_rst 15 arch/arm/mach-mmp/clock.h void __iomem *clk_rst; /* clock reset control register */ clk_rst 27 arch/arm/mach-mmp/clock.h .clk_rst = APBC_##_reg, \ clk_rst 35 arch/arm/mach-mmp/clock.h .clk_rst = APBC_##_reg, \ clk_rst 43 arch/arm/mach-mmp/clock.h .clk_rst = APMU_##_reg, \ clk_rst 51 arch/arm/mach-mmp/clock.h .clk_rst = APMU_##_reg, \ clk_rst 123 arch/arm/mach-mmp/mmp2.c unsigned long clk_rst; clk_rst 131 arch/arm/mach-mmp/mmp2.c clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); clk_rst 132 arch/arm/mach-mmp/mmp2.c __raw_writel(clk_rst, APBC_TIMERS);