clk_phase          43 drivers/clk/socfpga/clk-gate-a10.c 	u32 clk_phase[2];
clk_phase          45 drivers/clk/socfpga/clk-gate-a10.c 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
clk_phase          46 drivers/clk/socfpga/clk-gate-a10.c 		for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
clk_phase          47 drivers/clk/socfpga/clk-gate-a10.c 			switch (socfpgaclk->clk_phase[i]) {
clk_phase          49 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 0;
clk_phase          52 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 1;
clk_phase          55 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 2;
clk_phase          58 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 3;
clk_phase          61 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 4;
clk_phase          64 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 5;
clk_phase          67 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 6;
clk_phase          70 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 7;
clk_phase          73 drivers/clk/socfpga/clk-gate-a10.c 				clk_phase[i] = 0;
clk_phase          78 drivers/clk/socfpga/clk-gate-a10.c 		hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
clk_phase          99 drivers/clk/socfpga/clk-gate-a10.c 	u32 clk_phase[2];
clk_phase         139 drivers/clk/socfpga/clk-gate-a10.c 	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
clk_phase         141 drivers/clk/socfpga/clk-gate-a10.c 		socfpga_clk->clk_phase[0] = clk_phase[0];
clk_phase         142 drivers/clk/socfpga/clk-gate-a10.c 		socfpga_clk->clk_phase[1] = clk_phase[1];
clk_phase         117 drivers/clk/socfpga/clk-gate.c 	u32 clk_phase[2];
clk_phase         119 drivers/clk/socfpga/clk-gate.c 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
clk_phase         127 drivers/clk/socfpga/clk-gate.c 			switch (socfpgaclk->clk_phase[i]) {
clk_phase         129 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 0;
clk_phase         132 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 1;
clk_phase         135 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 2;
clk_phase         138 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 3;
clk_phase         141 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 4;
clk_phase         144 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 5;
clk_phase         147 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 6;
clk_phase         150 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 7;
clk_phase         153 drivers/clk/socfpga/clk-gate.c 				clk_phase[i] = 0;
clk_phase         157 drivers/clk/socfpga/clk-gate.c 		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
clk_phase         175 drivers/clk/socfpga/clk-gate.c 	u32 clk_phase[2];
clk_phase         220 drivers/clk/socfpga/clk-gate.c 	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
clk_phase         222 drivers/clk/socfpga/clk-gate.c 		socfpga_clk->clk_phase[0] = clk_phase[0];
clk_phase         223 drivers/clk/socfpga/clk-gate.c 		socfpga_clk->clk_phase[1] = clk_phase[1];
clk_phase          53 drivers/clk/socfpga/clk.h 	u32 clk_phase[2];
clk_phase         154 include/trace/events/clk.h DECLARE_EVENT_CLASS(clk_phase,
clk_phase         173 include/trace/events/clk.h DEFINE_EVENT(clk_phase, clk_set_phase,
clk_phase         180 include/trace/events/clk.h DEFINE_EVENT(clk_phase, clk_set_phase_complete,
clk_phase        1146 sound/soc/codecs/lm49453.c 	int clk_phase = 0;
clk_phase        1173 sound/soc/codecs/lm49453.c 		clk_phase = (1 << 5);
clk_phase        1178 sound/soc/codecs/lm49453.c 		clk_phase = (1 << 5);
clk_phase        1187 sound/soc/codecs/lm49453.c 			    (aif_val | mode | clk_phase));