clk_mux_uart1_p   252 drivers/clk/hisilicon/clk-hi3660.c clk_mux_uart1_p[] = {"clkin_sys", "clk_div_uart1",};
clk_mux_uart1_p   275 drivers/clk/hisilicon/clk-hi3660.c 	{ HI3660_CLK_MUX_UART1, "clk_mux_uart1", clk_mux_uart1_p,
clk_mux_uart1_p   276 drivers/clk/hisilicon/clk-hi3660.c 	  ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,