clk_mux_uart0_p   250 drivers/clk/hisilicon/clk-hi3660.c clk_mux_uart0_p[] = {"clkin_sys", "clk_div_uart0",};
clk_mux_uart0_p   272 drivers/clk/hisilicon/clk-hi3660.c 	{ HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
clk_mux_uart0_p   273 drivers/clk/hisilicon/clk-hi3660.c 	  ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
clk_mux_uart0_p   381 drivers/clk/hisilicon/clk-hi3670.c clk_mux_uart0_p[] = { "clkin_sys", "clk_div_uart0", };
clk_mux_uart0_p   448 drivers/clk/hisilicon/clk-hi3670.c 	{ HI3670_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
clk_mux_uart0_p   449 drivers/clk/hisilicon/clk-hi3670.c 	  ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT,