clk_mux_pcieaxi_p  387 drivers/clk/hisilicon/clk-hi3670.c clk_mux_pcieaxi_p[] = { "clkin_sys", "clk_ppll0", };
clk_mux_pcieaxi_p  457 drivers/clk/hisilicon/clk-hi3670.c 	{ HI3670_CLK_MUX_PCIEAXI, "clk_mux_pcieaxi", clk_mux_pcieaxi_p,
clk_mux_pcieaxi_p  458 drivers/clk/hisilicon/clk-hi3670.c 	  ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT,