clk_mux_ldi1_p    769 drivers/clk/hisilicon/clk-hi3670.c clk_mux_ldi1_p[] = { "clk_invalid", "clk_gate_ppll7_media",
clk_mux_ldi1_p    792 drivers/clk/hisilicon/clk-hi3670.c 	{ HI3670_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi1_p,
clk_mux_ldi1_p    793 drivers/clk/hisilicon/clk-hi3670.c 	  ARRAY_SIZE(clk_mux_ldi1_p), CLK_SET_RATE_PARENT,