clk_mux_ldi0_p    245 drivers/clk/hisilicon/clk-hi3660.c clk_mux_ldi0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll2", "clk_inv",
clk_mux_ldi0_p    290 drivers/clk/hisilicon/clk-hi3660.c 	{ HI3660_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi0_p,
clk_mux_ldi0_p    291 drivers/clk/hisilicon/clk-hi3660.c 	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
clk_mux_ldi0_p    293 drivers/clk/hisilicon/clk-hi3660.c 	{ HI3660_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
clk_mux_ldi0_p    294 drivers/clk/hisilicon/clk-hi3660.c 	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
clk_mux_ldi0_p    762 drivers/clk/hisilicon/clk-hi3670.c clk_mux_ldi0_p[] = { "clk_invalid", "clk_gate_ppll7_media",
clk_mux_ldi0_p    789 drivers/clk/hisilicon/clk-hi3670.c 	{ HI3670_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
clk_mux_ldi0_p    790 drivers/clk/hisilicon/clk-hi3670.c 	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT,