clk_mux_edc0_p    240 drivers/clk/hisilicon/clk-hi3660.c clk_mux_edc0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll1", "clk_inv",
clk_mux_edc0_p    302 drivers/clk/hisilicon/clk-hi3660.c 	{ HI3660_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
clk_mux_edc0_p    303 drivers/clk/hisilicon/clk-hi3660.c 	  ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
clk_mux_edc0_p    756 drivers/clk/hisilicon/clk-hi3670.c clk_mux_edc0_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
clk_mux_edc0_p    786 drivers/clk/hisilicon/clk-hi3670.c 	{ HI3670_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
clk_mux_edc0_p    787 drivers/clk/hisilicon/clk-hi3670.c 	  ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT,