clk_mgr_dce 114 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz) clk_mgr_dce 116 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { clk_mgr_dce 118 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage, clk_mgr_dce 119 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider), 200); clk_mgr_dce 157 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 159 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); clk_mgr_dce 198 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 207 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) clk_mgr_dce 209 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->max_clks_by_state[i].display_clk_khz clk_mgr_dce 211 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz) clk_mgr_dce 215 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (low_req_clk > clk_mgr_dce->max_clks_state) { clk_mgr_dce 217 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz clk_mgr_dce 221 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c low_req_clk = clk_mgr_dce->max_clks_state; clk_mgr_dce 233 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 237 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; clk_mgr_dce 242 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz / 64); clk_mgr_dce 248 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 253 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (clk_mgr_dce->dfs_bypass_active) { clk_mgr_dce 255 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dfs_bypass_disp_clk = clk_mgr_dce 263 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr_dce 272 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce) clk_mgr_dce 274 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; clk_mgr_dce 275 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; clk_mgr_dce 279 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; clk_mgr_dce 280 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (clk_mgr_dce->dentist_vco_freq_khz == 0) { clk_mgr_dce 281 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; clk_mgr_dce 282 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (clk_mgr_dce->dentist_vco_freq_khz == 0) clk_mgr_dce 283 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz = 3600000; clk_mgr_dce 316 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = clk_mgr_dce 322 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dfs_bypass_enabled = true; clk_mgr_dce 325 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce) clk_mgr_dce 327 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; clk_mgr_dce 343 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->ss_on_dprefclk = true; clk_mgr_dce 344 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; clk_mgr_dce 350 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_percentage = clk_mgr_dce 367 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->ss_on_dprefclk = true; clk_mgr_dce 368 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; clk_mgr_dce 374 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_percentage = clk_mgr_dce 399 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 404 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 409 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) clk_mgr_dce 410 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { clk_mgr_dce 412 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; clk_mgr_dce 33 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz); clk_mgr_dce 44 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h struct clk_mgr_internal *clk_mgr_dce); clk_mgr_dce 252 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 257 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 262 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) clk_mgr_dce 263 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { clk_mgr_dce 265 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; clk_mgr_dce 72 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 84 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz / 62); clk_mgr_dce 98 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr_dce 115 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock) clk_mgr_dce 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr_dce->dfs_bypass_disp_clk = actual_clock; clk_mgr_dce 197 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 202 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 207 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) clk_mgr_dce 208 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { clk_mgr_dce 210 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; clk_mgr_dce 56 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c static void dce121_clock_patch_xgmi_ss_info(struct clk_mgr_internal *clk_mgr_dce) clk_mgr_dce 60 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; clk_mgr_dce 62 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr_dce->xgmi_enabled = false; clk_mgr_dce 67 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr_dce->xgmi_enabled = true; clk_mgr_dce 68 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr_dce->ss_on_dprefclk = true; clk_mgr_dce 69 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider = clk_mgr_dce 78 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr_dce->dprefclk_ss_percentage = clk_mgr_dce 88 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr_dce 94 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 103 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c if (clk_mgr_dce->xgmi_enabled) clk_mgr_dce 105 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr_dce, patched_disp_clk); clk_mgr_dce 39 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c (clk_mgr_dce->regs->reg) clk_mgr_dce 43 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name clk_mgr_dce 46 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.ctx clk_mgr_dce 133 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz) clk_mgr_dce 135 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { clk_mgr_dce 137 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage, clk_mgr_dce 138 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider), 200); clk_mgr_dce 150 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 169 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c * clk_mgr_dce->dentist_vco_freq_khz) / target_div; clk_mgr_dce 171 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, dp_ref_clk_khz); clk_mgr_dce 176 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 178 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); clk_mgr_dce 217 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 226 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) clk_mgr_dce 228 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->max_clks_by_state[i].display_clk_khz clk_mgr_dce 230 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz) clk_mgr_dce 234 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (low_req_clk > clk_mgr_dce->max_clks_state) { clk_mgr_dce 236 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz clk_mgr_dce 240 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c low_req_clk = clk_mgr_dce->max_clks_state; clk_mgr_dce 250 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 254 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; clk_mgr_dce 259 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz / 64); clk_mgr_dce 265 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 270 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->dfs_bypass_active) { clk_mgr_dce 272 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dfs_bypass_disp_clk = clk_mgr_dce 280 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr_dce 290 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 302 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz / 62); clk_mgr_dce 314 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr_dce 331 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock) clk_mgr_dce 337 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dfs_bypass_disp_clk = actual_clock; clk_mgr_dce 341 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static void dce_clock_read_integrated_info(struct dce_clk_mgr *clk_mgr_dce) clk_mgr_dce 343 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; clk_mgr_dce 344 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; clk_mgr_dce 352 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq; clk_mgr_dce 353 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->dentist_vco_freq_khz == 0) { clk_mgr_dce 355 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz = clk_mgr_dce 357 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->dentist_vco_freq_khz == 0) clk_mgr_dce 358 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dentist_vco_freq_khz = 3600000; clk_mgr_dce 390 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = clk_mgr_dce 396 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dfs_bypass_enabled = true; clk_mgr_dce 399 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce) clk_mgr_dce 401 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; clk_mgr_dce 417 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->ss_on_dprefclk = true; clk_mgr_dce 418 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; clk_mgr_dce 424 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_percentage = clk_mgr_dce 441 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->ss_on_dprefclk = true; clk_mgr_dce 442 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; clk_mgr_dce 448 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_percentage = clk_mgr_dce 466 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 469 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; clk_mgr_dce 471 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->xgmi_enabled = false; clk_mgr_dce 476 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->xgmi_enabled = true; clk_mgr_dce 477 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->ss_on_dprefclk = true; clk_mgr_dce 478 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider = clk_mgr_dce 485 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_percentage = clk_mgr_dce 672 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 677 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 682 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) clk_mgr_dce 683 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { clk_mgr_dce 685 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; clk_mgr_dce 699 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 704 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 709 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) clk_mgr_dce 710 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { clk_mgr_dce 712 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; clk_mgr_dce 726 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 731 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 736 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) clk_mgr_dce 737 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { clk_mgr_dce 739 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; clk_mgr_dce 753 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr_dce 759 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (!clk_mgr_dce->dfs_bypass_active) clk_mgr_dce 768 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce->xgmi_enabled) clk_mgr_dce 770 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, patched_disp_clk); clk_mgr_dce 808 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce, clk_mgr_dce 814 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *base = &clk_mgr_dce->base; clk_mgr_dce 820 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->regs = regs; clk_mgr_dce 821 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->clk_mgr_shift = clk_shift; clk_mgr_dce 822 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->clk_mgr_mask = clk_mask; clk_mgr_dce 824 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dfs_bypass_disp_clk = 0; clk_mgr_dce 826 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_percentage = 0; clk_mgr_dce 827 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_ss_divider = 1000; clk_mgr_dce 828 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->ss_on_dprefclk = false; clk_mgr_dce 832 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state; clk_mgr_dce 834 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr_dce 835 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; clk_mgr_dce 837 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce_clock_read_integrated_info(clk_mgr_dce); clk_mgr_dce 838 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce_clock_read_ss_info(clk_mgr_dce); clk_mgr_dce 847 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); clk_mgr_dce 849 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce == NULL) { clk_mgr_dce 854 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c memcpy(clk_mgr_dce->max_clks_by_state, clk_mgr_dce 859 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, ctx, regs, clk_shift, clk_mask); clk_mgr_dce 861 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; clk_mgr_dce 870 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); clk_mgr_dce 872 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce == NULL) { clk_mgr_dce 877 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c memcpy(clk_mgr_dce->max_clks_by_state, clk_mgr_dce 882 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, ctx, regs, clk_shift, clk_mask); clk_mgr_dce 884 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce110_funcs; clk_mgr_dce 886 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; clk_mgr_dce 895 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); clk_mgr_dce 897 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce == NULL) { clk_mgr_dce 902 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c memcpy(clk_mgr_dce->max_clks_by_state, clk_mgr_dce 907 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, ctx, regs, clk_shift, clk_mask); clk_mgr_dce 909 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce112_funcs; clk_mgr_dce 911 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; clk_mgr_dce 916 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); clk_mgr_dce 918 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce == NULL) { clk_mgr_dce 923 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c memcpy(clk_mgr_dce->max_clks_by_state, clk_mgr_dce 928 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, ctx, NULL, NULL, NULL); clk_mgr_dce 930 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_khz = 600000; clk_mgr_dce 931 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce120_funcs; clk_mgr_dce 933 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; clk_mgr_dce 938 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), clk_mgr_dce 941 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (clk_mgr_dce == NULL) { clk_mgr_dce 946 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c memcpy(clk_mgr_dce->max_clks_by_state, dce120_max_clks_by_state, clk_mgr_dce 949 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce_clk_mgr_construct(clk_mgr_dce, ctx, NULL, NULL, NULL); clk_mgr_dce 951 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->dprefclk_khz = 625000; clk_mgr_dce 952 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce120_funcs; clk_mgr_dce 954 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; clk_mgr_dce 959 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr); clk_mgr_dce 961 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c kfree(clk_mgr_dce);