clk_mgr_base      146 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
clk_mgr_base      148 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      129 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
clk_mgr_base      131 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      155 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
clk_mgr_base      157 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      159 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
clk_mgr_base      195 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct clk_mgr *clk_mgr_base,
clk_mgr_base      198 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      230 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct clk_mgr *clk_mgr_base,
clk_mgr_base      233 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      235 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
clk_mgr_base      395 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base      399 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      407 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
clk_mgr_base      411 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
clk_mgr_base      415 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
clk_mgr_base      416 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
clk_mgr_base      417 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
clk_mgr_base      419 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
clk_mgr_base       34 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
clk_mgr_base       36 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h 	struct clk_mgr *clk_mgr_base,
clk_mgr_base       51 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h 	struct clk_mgr *clk_mgr_base,
clk_mgr_base      248 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c static void dce11_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base      252 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      260 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
clk_mgr_base      264 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
clk_mgr_base      268 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
clk_mgr_base      269 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);
clk_mgr_base      270 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
clk_mgr_base      272 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
clk_mgr_base       70 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
clk_mgr_base       72 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base       74 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
clk_mgr_base       75 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dc *core_dc = clk_mgr_base->ctx->dc;
clk_mgr_base      104 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
clk_mgr_base      193 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base      197 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      205 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
clk_mgr_base      209 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
clk_mgr_base      213 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
clk_mgr_base      214 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk);
clk_mgr_base      215 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
clk_mgr_base      217 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
clk_mgr_base       35 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
clk_mgr_base       84 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c static void dce12_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base       88 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base       97 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
clk_mgr_base      107 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 		clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk);
clk_mgr_base      109 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 		dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req);
clk_mgr_base      112 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) {
clk_mgr_base      115 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 		clk_mgr_base->clks.phyclk_khz = max_pix_clk;
clk_mgr_base      117 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 		dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req);
clk_mgr_base      119 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
clk_mgr_base      125 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base      129 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      130 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
clk_mgr_base      159 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz
clk_mgr_base      160 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			|| new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz
clk_mgr_base      161 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			|| new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz
clk_mgr_base      162 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			|| new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz)
clk_mgr_base      165 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
clk_mgr_base      166 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
clk_mgr_base      174 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
clk_mgr_base      175 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
clk_mgr_base      180 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
clk_mgr_base      181 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
clk_mgr_base      186 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
clk_mgr_base      187 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
clk_mgr_base      207 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)
clk_mgr_base      208 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			|| new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) {
clk_mgr_base      210 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
clk_mgr_base      226 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
clk_mgr_base      228 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base       52 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base)
clk_mgr_base       54 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      143 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
clk_mgr_base      145 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      146 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
clk_mgr_base      156 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
clk_mgr_base      161 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
clk_mgr_base      164 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
clk_mgr_base      166 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      167 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
clk_mgr_base      178 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
clk_mgr_base      183 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
clk_mgr_base      186 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base      190 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      192 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
clk_mgr_base      197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
clk_mgr_base      204 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (clk_mgr_base->clks.dispclk_khz == 0 ||
clk_mgr_base      222 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
clk_mgr_base      223 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
clk_mgr_base      225 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
clk_mgr_base      233 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
clk_mgr_base      234 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
clk_mgr_base      236 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
clk_mgr_base      240 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
clk_mgr_base      241 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
clk_mgr_base      243 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
clk_mgr_base      246 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
clk_mgr_base      247 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
clk_mgr_base      249 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
clk_mgr_base      252 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
clk_mgr_base      253 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
clk_mgr_base      255 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
clk_mgr_base      257 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
clk_mgr_base      259 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
clk_mgr_base      261 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
clk_mgr_base      262 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
clk_mgr_base      264 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
clk_mgr_base      269 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz))
clk_mgr_base      270 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz);
clk_mgr_base      277 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz)
clk_mgr_base      278 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
clk_mgr_base      295 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz)
clk_mgr_base      296 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
clk_mgr_base      315 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
clk_mgr_base      385 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
clk_mgr_base      387 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base       55 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void rn_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base       59 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base       61 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct dc *dc = clk_mgr_base->ctx->dc;
clk_mgr_base       67 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
clk_mgr_base       78 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
clk_mgr_base       79 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
clk_mgr_base       80 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
clk_mgr_base       83 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
clk_mgr_base       84 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
clk_mgr_base       85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
clk_mgr_base       89 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
clk_mgr_base       90 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
clk_mgr_base       91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
clk_mgr_base      103 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
clk_mgr_base      107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
clk_mgr_base      108 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
clk_mgr_base      109 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
clk_mgr_base      117 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
clk_mgr_base      121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
clk_mgr_base      130 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
clk_mgr_base      166 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
clk_mgr_base      168 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
clk_mgr_base      188 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
clk_mgr_base      195 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	rn_dump_clk_registers_internal(&internal, clk_mgr_base);
clk_mgr_base      321 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
clk_mgr_base      326 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
clk_mgr_base      331 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
clk_mgr_base      333 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);