clk_level_info    278 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		struct dm_pp_clock_levels_with_latency *clk_level_info,
clk_level_info    289 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
clk_level_info    291 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = pp_clks->num_levels;
clk_level_info    296 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	for (i = 0; i < clk_level_info->num_levels; i++) {
clk_level_info    298 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
clk_level_info    299 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
clk_level_info    305 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		struct dm_pp_clock_levels_with_voltage *clk_level_info,
clk_level_info    316 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
clk_level_info    318 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = pp_clks->num_levels;
clk_level_info    323 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	for (i = 0; i < clk_level_info->num_levels; i++) {
clk_level_info    326 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
clk_level_info    327 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
clk_level_info    420 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct dm_pp_clock_levels_with_latency *clk_level_info)
clk_level_info    442 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
clk_level_info    450 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct dm_pp_clock_levels_with_voltage *clk_level_info)
clk_level_info    471 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
clk_level_info    201 drivers/gpu/drm/amd/display/dc/dm_services.h 	struct dm_pp_clock_levels *clk_level_info);
clk_level_info    206 drivers/gpu/drm/amd/display/dc/dm_services.h 	struct dm_pp_clock_levels_with_latency *clk_level_info);
clk_level_info    211 drivers/gpu/drm/amd/display/dc/dm_services.h 	struct dm_pp_clock_levels_with_voltage *clk_level_info);