clk_lane_reg1 100 drivers/media/i2c/st-mipid02.c u8 clk_lane_reg1; clk_lane_reg1 404 drivers/media/i2c/st-mipid02.c bridge->r.clk_lane_reg1 |= (2000000000 / link_freq) << 2; clk_lane_reg1 420 drivers/media/i2c/st-mipid02.c bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE; clk_lane_reg1 564 drivers/media/i2c/st-mipid02.c bridge->r.clk_lane_reg1);