clk_enet_ref_table 94 drivers/clk/imx/clk-imx6q.c static struct clk_div_table clk_enet_ref_table[] = { clk_enet_ref_table 548 drivers/clk/imx/clk-imx6q.c base + 0xe0, 0, 2, 0, clk_enet_ref_table, clk_enet_ref_table 70 drivers/clk/imx/clk-imx6sl.c static const struct clk_div_table clk_enet_ref_table[] = { clk_enet_ref_table 276 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); clk_enet_ref_table 87 drivers/clk/imx/clk-imx6sx.c static const struct clk_div_table clk_enet_ref_table[] = { clk_enet_ref_table 226 drivers/clk/imx/clk-imx6sx.c base + 0xe0, 0, 2, 0, clk_enet_ref_table, clk_enet_ref_table 229 drivers/clk/imx/clk-imx6sx.c base + 0xe0, 2, 2, 0, clk_enet_ref_table, clk_enet_ref_table 74 drivers/clk/imx/clk-imx6ul.c static const struct clk_div_table clk_enet_ref_table[] = { clk_enet_ref_table 210 drivers/clk/imx/clk-imx6ul.c base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); clk_enet_ref_table 212 drivers/clk/imx/clk-imx6ul.c base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);