clk_divider_ops 795 drivers/clk/bcm/clk-bcm2835.c return clk_divider_ops.round_rate(hw, rate, parent_rate); clk_divider_ops 801 drivers/clk/bcm/clk-bcm2835.c return clk_divider_ops.recalc_rate(hw, parent_rate); clk_divider_ops 453 drivers/clk/clk-divider.c const struct clk_ops clk_divider_ops = { clk_divider_ops 458 drivers/clk/clk-divider.c EXPORT_SYMBOL_GPL(clk_divider_ops); clk_divider_ops 493 drivers/clk/clk-divider.c init.ops = &clk_divider_ops; clk_divider_ops 709 drivers/clk/clk-stm32f4.c return clk_divider_ops.recalc_rate(hw, parent_rate); clk_divider_ops 715 drivers/clk/clk-stm32f4.c return clk_divider_ops.round_rate(hw, rate, prate); clk_divider_ops 731 drivers/clk/clk-stm32f4.c ret = clk_divider_ops.set_rate(hw, rate, parent_rate); clk_divider_ops 396 drivers/clk/clk-stm32h7.c gcfg->div->ops : &clk_divider_ops; clk_divider_ops 845 drivers/clk/clk-stm32h7.c return clk_divider_ops.recalc_rate(hw, parent_rate); clk_divider_ops 851 drivers/clk/clk-stm32h7.c return clk_divider_ops.round_rate(hw, rate, prate); clk_divider_ops 868 drivers/clk/clk-stm32h7.c ret = clk_divider_ops.set_rate(hw, rate, parent_rate); clk_divider_ops 640 drivers/clk/clk-stm32mp1.c div_ops = &clk_divider_ops; clk_divider_ops 242 drivers/clk/davinci/pll.c const struct clk_ops *divider_ops = &clk_divider_ops; clk_divider_ops 619 drivers/clk/davinci/pll.c ÷r->hw, &clk_divider_ops, clk_divider_ops 681 drivers/clk/davinci/pll.c const struct clk_ops *divider_ops = &clk_divider_ops; clk_divider_ops 95 drivers/clk/imx/clk-busy.c busy->div_ops = &clk_divider_ops; clk_divider_ops 70 drivers/clk/imx/clk-divider-gate.c return clk_divider_ops.round_rate(hw, rate, prate); clk_divider_ops 115 drivers/clk/imx/clk-fixup-div.c fixup_div->ops = &clk_divider_ops; clk_divider_ops 213 drivers/clk/mediatek/clk-mtk.c div_ops = &clk_divider_ops; clk_divider_ops 96 drivers/clk/mxs/clk-div.c div->ops = &clk_divider_ops; clk_divider_ops 549 drivers/clk/nxp/clk-lpc18xx-cgu.c &clk->div.hw, &clk_divider_ops, clk_divider_ops 236 drivers/clk/renesas/clk-rcar-gen2.c &div->hw, &clk_divider_ops, clk_divider_ops 235 drivers/clk/renesas/rcar-gen2-cpg.c &div->hw, &clk_divider_ops, clk_divider_ops 466 drivers/clk/renesas/rcar-gen3-cpg.c &rpc->div.hw, &clk_divider_ops, clk_divider_ops 100 drivers/clk/rockchip/clk.c : &clk_divider_ops; clk_divider_ops 142 drivers/clk/st/clk-flexgen.c mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate); clk_divider_ops 144 drivers/clk/st/clk-flexgen.c return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate); clk_divider_ops 177 drivers/clk/st/clk-flexgen.c clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); clk_divider_ops 178 drivers/clk/st/clk-flexgen.c ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); clk_divider_ops 180 drivers/clk/st/clk-flexgen.c clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); clk_divider_ops 181 drivers/clk/st/clk-flexgen.c ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); clk_divider_ops 674 drivers/clk/st/clkgen-pll.c &div->hw, &clk_divider_ops, clk_divider_ops 122 drivers/clk/sunxi/clk-a10-ve.c &div->hw, &clk_divider_ops, clk_divider_ops 161 drivers/clk/sunxi/clk-sun4i-display.c data->has_div ? &clk_divider_ops : NULL, clk_divider_ops 79 drivers/clk/sunxi/clk-sun8i-mbus.c &div->hw, &clk_divider_ops, clk_divider_ops 1073 drivers/clk/sunxi/clk-sunxi.c rate_ops = &clk_divider_ops; clk_divider_ops 133 drivers/clk/zte/clk.h &clk_divider_ops, \ clk_divider_ops 664 drivers/iio/adc/meson_saradc.c init.ops = &clk_divider_ops; clk_divider_ops 467 drivers/mmc/host/meson-gx-mmc.c init.ops = &clk_divider_ops; clk_divider_ops 609 drivers/mmc/host/meson-mx-sdio.c init.ops = &clk_divider_ops; clk_divider_ops 162 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c &clk_divider_ops, clk_divider_ops 468 include/linux/clk-provider.h extern const struct clk_ops clk_divider_ops;