clk_desc 46 drivers/clk/clk-palmas.c const struct palmas_clk32k_desc *clk_desc; clk_desc 67 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, clk_desc 68 drivers/clk/clk-palmas.c cinfo->clk_desc->enable_mask, clk_desc 69 drivers/clk/clk-palmas.c cinfo->clk_desc->enable_mask); clk_desc 72 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); clk_desc 73 drivers/clk/clk-palmas.c else if (cinfo->clk_desc->delay) clk_desc 74 drivers/clk/clk-palmas.c udelay(cinfo->clk_desc->delay); clk_desc 92 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, clk_desc 93 drivers/clk/clk-palmas.c cinfo->clk_desc->enable_mask, 0); clk_desc 96 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); clk_desc 109 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, &val); clk_desc 112 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); clk_desc 115 drivers/clk/clk-palmas.c return !!(val & cinfo->clk_desc->enable_mask); clk_desc 211 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, clk_desc 212 drivers/clk/clk-palmas.c cinfo->clk_desc->sleep_mask, 0); clk_desc 215 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); clk_desc 227 drivers/clk/clk-palmas.c cinfo->clk_desc->sleep_reqstr_id, clk_desc 231 drivers/clk/clk-palmas.c cinfo->clk_desc->clk_name, ret); clk_desc 261 drivers/clk/clk-palmas.c cinfo->clk_desc = &match_data->desc; clk_desc 133 drivers/firmware/arm_scmi/clock.c struct scmi_msg_clock_describe_rates *clk_desc; clk_desc 137 drivers/firmware/arm_scmi/clock.c SCMI_PROTOCOL_CLOCK, sizeof(*clk_desc), 0, &t); clk_desc 141 drivers/firmware/arm_scmi/clock.c clk_desc = t->tx.buf; clk_desc 145 drivers/firmware/arm_scmi/clock.c clk_desc->id = cpu_to_le32(clk_id); clk_desc 147 drivers/firmware/arm_scmi/clock.c clk_desc->rate_index = cpu_to_le32(tot_rate_cnt);