clk_ctrls          69 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
clk_ctrls          71 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
clk_ctrls          73 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
clk_ctrls          75 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
clk_ctrls          77 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
clk_ctrls          79 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
clk_ctrls          81 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
clk_ctrls          83 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
clk_ctrls         422 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
clk_ctrls         108 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
clk_ctrls         109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;