clk_ctrl          238 arch/mips/ath79/clock.c 	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
clk_ctrl          307 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
clk_ctrl          309 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
clk_ctrl          312 arch/mips/ath79/clock.c 	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
clk_ctrl          314 arch/mips/ath79/clock.c 	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
clk_ctrl          319 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
clk_ctrl          322 arch/mips/ath79/clock.c 	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
clk_ctrl          324 arch/mips/ath79/clock.c 	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
clk_ctrl          329 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
clk_ctrl          332 arch/mips/ath79/clock.c 	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
clk_ctrl          334 arch/mips/ath79/clock.c 	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
clk_ctrl          343 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
clk_ctrl          344 arch/mips/ath79/clock.c 	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
clk_ctrl          356 arch/mips/ath79/clock.c 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
clk_ctrl          396 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
clk_ctrl          398 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
clk_ctrl          401 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
clk_ctrl          403 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
clk_ctrl          408 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
clk_ctrl          411 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
clk_ctrl          413 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
clk_ctrl          418 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
clk_ctrl          421 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
clk_ctrl          423 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
clk_ctrl          439 arch/mips/ath79/clock.c 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
clk_ctrl          479 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
clk_ctrl          481 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
clk_ctrl          484 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
clk_ctrl          486 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
clk_ctrl          491 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
clk_ctrl          494 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
clk_ctrl          496 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
clk_ctrl          501 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
clk_ctrl          504 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
clk_ctrl          506 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
clk_ctrl          522 arch/mips/ath79/clock.c 	u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
clk_ctrl          581 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
clk_ctrl          583 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
clk_ctrl          586 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
clk_ctrl          588 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
clk_ctrl          593 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
clk_ctrl          596 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
clk_ctrl          598 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
clk_ctrl          603 arch/mips/ath79/clock.c 	postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
clk_ctrl          606 arch/mips/ath79/clock.c 	if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
clk_ctrl          608 arch/mips/ath79/clock.c 	else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
clk_ctrl          729 drivers/clk/bcm/clk-iproc-pll.c 			 const struct iproc_clk_ctrl *clk_ctrl,
clk_ctrl          740 drivers/clk/bcm/clk-iproc-pll.c 	if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl))
clk_ctrl          821 drivers/clk/bcm/clk-iproc-pll.c 		iclk->ctrl = &clk_ctrl[i];
clk_ctrl          217 drivers/clk/bcm/clk-iproc.h 			 const struct iproc_clk_ctrl *clk_ctrl,
clk_ctrl          176 drivers/clk/zynq/clkc.c 		const char *clk_name1, void __iomem *clk_ctrl,
clk_ctrl          193 drivers/clk/zynq/clkc.c 			CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
clk_ctrl          195 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
clk_ctrl          199 drivers/clk/zynq/clkc.c 			CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
clk_ctrl          202 drivers/clk/zynq/clkc.c 				CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
clk_ctrl          184 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.clk_ctrl = _clkctrl \
clk_ctrl          448 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 	enum dpu_clk_ctrl_type clk_ctrl;
clk_ctrl           93 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 		enum dpu_clk_ctrl_type clk_ctrl, bool enable)
clk_ctrl          105 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX)
clk_ctrl          108 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
clk_ctrl          109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
clk_ctrl          103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h 			enum dpu_clk_ctrl_type clk_ctrl, bool enable);
clk_ctrl          384 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
clk_ctrl          402 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
clk_ctrl          411 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			qos_params.clk_ctrl);
clk_ctrl         1371 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			(u32 *) &cfg->clk_ctrl);
clk_ctrl          192 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
clk_ctrl          205 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 		mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false);
clk_ctrl          249 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
clk_ctrl          260 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 		mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false);
clk_ctrl           19 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h 	u32 clk_ctrl;
clk_ctrl           25 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h 	u32 clk_ctrl;
clk_ctrl           40 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h 	u32 clk_ctrl;
clk_ctrl          358 drivers/mmc/host/sdhci-tegra.c 	u32 misc_ctrl, clk_ctrl, pad_ctrl;
clk_ctrl          368 drivers/mmc/host/sdhci-tegra.c 	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
clk_ctrl          375 drivers/mmc/host/sdhci-tegra.c 	clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
clk_ctrl          390 drivers/mmc/host/sdhci-tegra.c 			clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
clk_ctrl          393 drivers/mmc/host/sdhci-tegra.c 	clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
clk_ctrl          396 drivers/mmc/host/sdhci-tegra.c 	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
clk_ctrl          197 drivers/net/wireless/st/cw1200/cw1200_sdio.c 	if (pdata->clk_ctrl)
clk_ctrl          198 drivers/net/wireless/st/cw1200/cw1200_sdio.c 		pdata->clk_ctrl(pdata, false);
clk_ctrl          226 drivers/net/wireless/st/cw1200/cw1200_sdio.c 	if (pdata->clk_ctrl) {
clk_ctrl          227 drivers/net/wireless/st/cw1200/cw1200_sdio.c 		if (pdata->clk_ctrl(pdata, true)) {
clk_ctrl          292 drivers/net/wireless/st/cw1200/cw1200_spi.c 	if (pdata->clk_ctrl)
clk_ctrl          293 drivers/net/wireless/st/cw1200/cw1200_spi.c 		pdata->clk_ctrl(pdata, false);
clk_ctrl          321 drivers/net/wireless/st/cw1200/cw1200_spi.c 	if (pdata->clk_ctrl) {
clk_ctrl          322 drivers/net/wireless/st/cw1200/cw1200_spi.c 		if (pdata->clk_ctrl(pdata, true)) {
clk_ctrl           21 include/linux/platform_data/net-cw1200.h 	int (*clk_ctrl)(const struct cw1200_platform_data_spi *pdata,
clk_ctrl           38 include/linux/platform_data/net-cw1200.h 	int (*clk_ctrl)(const struct cw1200_platform_data_sdio *pdata,
clk_ctrl          362 sound/soc/codecs/pcm186x.c 	u8 clk_ctrl = 0;
clk_ctrl          374 sound/soc/codecs/pcm186x.c 		clk_ctrl |= PCM186X_CLK_CTRL_MST_MODE;
clk_ctrl          418 sound/soc/codecs/pcm186x.c 			    PCM186X_CLK_CTRL_MST_MODE, clk_ctrl);