clk_activity_offset 2774 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
clk_activity_offset 2789 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				clk_activity_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
clk_activity_offset 2791 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 2793 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
clk_activity_offset 2824 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				clk_activity_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
clk_activity_offset 2826 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 2828 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
clk_activity_offset 2566 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
clk_activity_offset 2581 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				clk_activity_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
clk_activity_offset 2583 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 2585 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
clk_activity_offset 2616 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				clk_activity_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
clk_activity_offset 2618 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 2620 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
clk_activity_offset 2479 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
clk_activity_offset 2494 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
clk_activity_offset 2496 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 2498 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
clk_activity_offset 2529 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
clk_activity_offset 2531 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 2533 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
clk_activity_offset 3162 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
clk_activity_offset 3177 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				clk_activity_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
clk_activity_offset 3179 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 3181 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
clk_activity_offset 3212 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				clk_activity_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
clk_activity_offset 3214 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				offset = clk_activity_offset & ~0x3;
clk_activity_offset 3216 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));