CUR_CONTROL 2289 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); CUR_CONTROL 2305 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); CUR_CONTROL 2306 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); CUR_CONTROL 2368 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); CUR_CONTROL 2384 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); CUR_CONTROL 2385 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); CUR_CONTROL 55 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); CUR_CONTROL 98 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_UPDATE_3(CUR_CONTROL, CUR_CONTROL 36 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_CONTROL, DCP, id), \ CUR_CONTROL 69 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \ CUR_CONTROL 70 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \ CUR_CONTROL 71 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ CUR_CONTROL 72 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ CUR_CONTROL 200 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t CUR_CONTROL;