ck_dpll1 81 arch/arm/mach-omap1/clock_data.c static struct clk ck_dpll1 = { ck_dpll1 95 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 119 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 130 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 149 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 211 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 223 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 233 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 264 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 384 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 397 arch/arm/mach-omap1/clock_data.c .parent = &ck_dpll1, ck_dpll1 673 arch/arm/mach-omap1/clock_data.c CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), ck_dpll1 757 arch/arm/mach-omap1/clock_data.c ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, ck_dpll1 834 arch/arm/mach-omap1/clock_data.c ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ ck_dpll1 838 arch/arm/mach-omap1/clock_data.c ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; ck_dpll1 839 arch/arm/mach-omap1/clock_data.c ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; ck_dpll1 846 arch/arm/mach-omap1/clock_data.c ck_dpll1.rate /= 2; ck_dpll1 849 arch/arm/mach-omap1/clock_data.c ck_dpll1.rate /= 4; ck_dpll1 854 arch/arm/mach-omap1/clock_data.c propagate_rate(&ck_dpll1); ck_dpll1 907 arch/arm/mach-omap1/clock_data.c unsigned long rate = ck_dpll1.rate; ck_dpll1 916 arch/arm/mach-omap1/clock_data.c ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; ck_dpll1 918 arch/arm/mach-omap1/clock_data.c propagate_rate(&ck_dpll1); ck_dpll1 920 arch/arm/mach-omap1/clock_data.c loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);