ciu_qlm          1240 arch/mips/pci/pcie-octeon.c 			union cvmx_ciu_qlm ciu_qlm;
ciu_qlm          1241 arch/mips/pci/pcie-octeon.c 			ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
ciu_qlm          1242 arch/mips/pci/pcie-octeon.c 			ciu_qlm.s.txbypass = 1;
ciu_qlm          1243 arch/mips/pci/pcie-octeon.c 			ciu_qlm.s.txdeemph = 5;
ciu_qlm          1244 arch/mips/pci/pcie-octeon.c 			ciu_qlm.s.txmargin = 0x17;
ciu_qlm          1245 arch/mips/pci/pcie-octeon.c 			cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
ciu_qlm          1247 arch/mips/pci/pcie-octeon.c 			union cvmx_ciu_qlm ciu_qlm;
ciu_qlm          1248 arch/mips/pci/pcie-octeon.c 			ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
ciu_qlm          1249 arch/mips/pci/pcie-octeon.c 			ciu_qlm.s.txbypass = 1;
ciu_qlm          1250 arch/mips/pci/pcie-octeon.c 			ciu_qlm.s.txdeemph = 5;
ciu_qlm          1251 arch/mips/pci/pcie-octeon.c 			ciu_qlm.s.txmargin = 0x17;
ciu_qlm          1252 arch/mips/pci/pcie-octeon.c 			cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);