chv_dpll_md      1462 drivers/gpu/drm/i915/display/intel_display.c 		dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
chv_dpll_md      8831 drivers/gpu/drm/i915/display/intel_display.c 			tmp = dev_priv->chv_dpll_md[crtc->pipe];
chv_dpll_md      1562 drivers/gpu/drm/i915/i915_drv.h 	u32 chv_dpll_md[I915_MAX_PIPES];