chunk_hdl_adjust_cur1 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, chunk_hdl_adjust_cur1 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, chunk_hdl_adjust_cur1 1511 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; chunk_hdl_adjust_cur1 1511 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; chunk_hdl_adjust_cur1 1611 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; chunk_hdl_adjust_cur1 444 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int chunk_hdl_adjust_cur1; chunk_hdl_adjust_cur1 308 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.chunk_hdl_adjust_cur1);