chunk_hdl_adjust_cur0 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, chunk_hdl_adjust_cur0 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, chunk_hdl_adjust_cur0 1509 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; chunk_hdl_adjust_cur0 1509 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; chunk_hdl_adjust_cur0 1609 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; chunk_hdl_adjust_cur0 443 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int chunk_hdl_adjust_cur0; chunk_hdl_adjust_cur0 302 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.chunk_hdl_adjust_cur0); chunk_hdl_adjust_cur0 1723 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;