chip_mbox 1450 arch/mips/cavium-octeon/octeon-irq.c struct irq_chip *chip_mbox; chip_mbox 1480 arch/mips/cavium-octeon/octeon-irq.c chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_mbox 1486 arch/mips/cavium-octeon/octeon-irq.c chip_mbox = &octeon_irq_chip_ciu_mbox; chip_mbox 1509 arch/mips/cavium-octeon/octeon-irq.c OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq); chip_mbox 1513 arch/mips/cavium-octeon/octeon-irq.c OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);