chcr               93 arch/sh/drivers/dma/dma-sh.c 	u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
chcr               94 arch/sh/drivers/dma/dma-sh.c 	int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
chcr               95 arch/sh/drivers/dma/dma-sh.c 		((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
chcr              109 arch/sh/drivers/dma/dma-sh.c 	u32 chcr;
chcr              111 arch/sh/drivers/dma/dma-sh.c 	chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
chcr              113 arch/sh/drivers/dma/dma-sh.c 	if (!(chcr & CHCR_TE))
chcr              116 arch/sh/drivers/dma/dma-sh.c 	chcr &= ~(CHCR_IE | CHCR_DE);
chcr              117 arch/sh/drivers/dma/dma-sh.c 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
chcr              139 arch/sh/drivers/dma/dma-sh.c sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
chcr              141 arch/sh/drivers/dma/dma-sh.c 	if (!chcr)
chcr              142 arch/sh/drivers/dma/dma-sh.c 		chcr = RS_DUAL | CHCR_IE;
chcr              144 arch/sh/drivers/dma/dma-sh.c 	if (chcr & CHCR_IE) {
chcr              145 arch/sh/drivers/dma/dma-sh.c 		chcr &= ~CHCR_IE;
chcr              151 arch/sh/drivers/dma/dma-sh.c 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
chcr              160 arch/sh/drivers/dma/dma-sh.c 	u32 chcr;
chcr              162 arch/sh/drivers/dma/dma-sh.c 	chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
chcr              163 arch/sh/drivers/dma/dma-sh.c 	chcr |= CHCR_DE;
chcr              166 arch/sh/drivers/dma/dma-sh.c 		chcr |= CHCR_IE;
chcr              168 arch/sh/drivers/dma/dma-sh.c 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
chcr              179 arch/sh/drivers/dma/dma-sh.c 	u32 chcr;
chcr              186 arch/sh/drivers/dma/dma-sh.c 	chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
chcr              187 arch/sh/drivers/dma/dma-sh.c 	chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
chcr              188 arch/sh/drivers/dma/dma-sh.c 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
chcr               30 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               35 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               40 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               45 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               50 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               55 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               60 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr               65 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr               70 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr               75 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr               80 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
chcr               85 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
chcr               36 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               41 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               46 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               51 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               56 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               61 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               66 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               71 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               76 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               81 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               86 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               91 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
chcr               96 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              101 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              106 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              111 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              116 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              121 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              126 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              131 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
chcr              136 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
chcr              141 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
chcr              146 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
chcr              151 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
chcr              120 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              127 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              134 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              141 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              151 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              158 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              165 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              172 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              179 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              186 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              193 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              200 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              210 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              217 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              224 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              231 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              238 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              245 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              252 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              259 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              266 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              273 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              283 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              290 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              297 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              304 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              311 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              318 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              325 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              332 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr              339 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
chcr              346 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= DM_INC | RS_ERS | 0x40000000 |
chcr               76 drivers/dma/sh/rcar-dmac.c 	u32 chcr;
chcr              334 drivers/dma/sh/rcar-dmac.c 	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
chcr              336 drivers/dma/sh/rcar-dmac.c 	return !!(chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE));
chcr              342 drivers/dma/sh/rcar-dmac.c 	u32 chcr = desc->chcr;
chcr              389 drivers/dma/sh/rcar-dmac.c 		chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR
chcr              397 drivers/dma/sh/rcar-dmac.c 			chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE;
chcr              403 drivers/dma/sh/rcar-dmac.c 			chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE;
chcr              409 drivers/dma/sh/rcar-dmac.c 			chcr |= RCAR_DMACHCR_DPM_INFINITE;
chcr              431 drivers/dma/sh/rcar-dmac.c 		chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
chcr              435 drivers/dma/sh/rcar-dmac.c 			     chcr | RCAR_DMACHCR_DE | RCAR_DMACHCR_CAIE);
chcr              748 drivers/dma/sh/rcar-dmac.c 	u32 chcr;
chcr              756 drivers/dma/sh/rcar-dmac.c 		chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
chcr              757 drivers/dma/sh/rcar-dmac.c 		if (!(chcr & RCAR_DMACHCR_DE))
chcr              767 drivers/dma/sh/rcar-dmac.c 	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
chcr              770 drivers/dma/sh/rcar-dmac.c 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, (chcr & ~RCAR_DMACHCR_DE));
chcr              778 drivers/dma/sh/rcar-dmac.c 	u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
chcr              780 drivers/dma/sh/rcar-dmac.c 	chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
chcr              783 drivers/dma/sh/rcar-dmac.c 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
chcr              856 drivers/dma/sh/rcar-dmac.c 	u32 chcr;
chcr              860 drivers/dma/sh/rcar-dmac.c 		chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED
chcr              866 drivers/dma/sh/rcar-dmac.c 		chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC
chcr              873 drivers/dma/sh/rcar-dmac.c 		chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC
chcr              880 drivers/dma/sh/rcar-dmac.c 	desc->chcr = chcr | chcr_ts[desc->xfer_shift];
chcr             1549 drivers/dma/sh/rcar-dmac.c 	u32 chcr;
chcr             1553 drivers/dma/sh/rcar-dmac.c 	chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
chcr             1554 drivers/dma/sh/rcar-dmac.c 	if (chcr & RCAR_DMACHCR_CAE) {
chcr             1568 drivers/dma/sh/rcar-dmac.c 	if (chcr & RCAR_DMACHCR_TE)
chcr             1570 drivers/dma/sh/rcar-dmac.c 	rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
chcr             1574 drivers/dma/sh/rcar-dmac.c 	if (chcr & RCAR_DMACHCR_DSE)
chcr             1577 drivers/dma/sh/rcar-dmac.c 	if (chcr & RCAR_DMACHCR_TE)
chcr              177 drivers/dma/sh/shdmac.c 	u32 chcr = chcr_read(sh_chan);
chcr              179 drivers/dma/sh/shdmac.c 	if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
chcr              185 drivers/dma/sh/shdmac.c static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
chcr              189 drivers/dma/sh/shdmac.c 	int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
chcr              190 drivers/dma/sh/shdmac.c 		((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
chcr              225 drivers/dma/sh/shdmac.c 	u32 chcr = chcr_read(sh_chan);
chcr              230 drivers/dma/sh/shdmac.c 	chcr |= CHCR_DE | shdev->chcr_ie_bit;
chcr              231 drivers/dma/sh/shdmac.c 	chcr_write(sh_chan, chcr & ~CHCR_TE);
chcr              239 drivers/dma/sh/shdmac.c 	u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,
chcr              241 drivers/dma/sh/shdmac.c 	sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
chcr              242 drivers/dma/sh/shdmac.c 	chcr_write(sh_chan, chcr);
chcr              315 drivers/dma/sh/shdmac.c 		dmae_set_chcr(sh_chan, cfg->chcr);
chcr              371 drivers/dma/sh/shdmac.c 	u32 chcr = chcr_read(sh_chan);
chcr              373 drivers/dma/sh/shdmac.c 	chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
chcr              374 drivers/dma/sh/shdmac.c 	chcr_write(sh_chan, chcr);
chcr              620 drivers/dma/sh/shdmac.c 			dmae_set_chcr(sh_chan, cfg->chcr);
chcr              177 drivers/dma/sh/usb-dmac.c 	u32 chcr = usb_dmac_chan_read(chan, USB_DMACHCR);
chcr              179 drivers/dma/sh/usb-dmac.c 	return (chcr & (USB_DMACHCR_DE | USB_DMACHCR_TE)) == USB_DMACHCR_DE;
chcr              364 drivers/dma/sh/usb-dmac.c 	u32 chcr = usb_dmac_chan_read(chan, USB_DMACHCR);
chcr              366 drivers/dma/sh/usb-dmac.c 	chcr &= ~(USB_DMACHCR_IE | USB_DMACHCR_TE | USB_DMACHCR_DE);
chcr              367 drivers/dma/sh/usb-dmac.c 	usb_dmac_chan_write(chan, USB_DMACHCR, chcr);
chcr              601 drivers/dma/sh/usb-dmac.c 	u32 chcr;
chcr              606 drivers/dma/sh/usb-dmac.c 	chcr = usb_dmac_chan_read(chan, USB_DMACHCR);
chcr              607 drivers/dma/sh/usb-dmac.c 	if (chcr & (USB_DMACHCR_TE | USB_DMACHCR_SP)) {
chcr              609 drivers/dma/sh/usb-dmac.c 		if (chcr & USB_DMACHCR_DE)
chcr              613 drivers/dma/sh/usb-dmac.c 	if (chcr & USB_DMACHCR_NULL) {
chcr              616 drivers/dma/sh/usb-dmac.c 		chcr |= USB_DMACHCR_FTE;
chcr              620 drivers/dma/sh/usb-dmac.c 		usb_dmac_chan_write(chan, USB_DMACHCR, chcr & ~mask);
chcr              480 drivers/staging/comedi/drivers/mite.c 	unsigned int chcr, mcr, dcr, lkcr;
chcr              485 drivers/staging/comedi/drivers/mite.c 	chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
chcr              495 drivers/staging/comedi/drivers/mite.c 	chcr |= CHCR_SET_LC_IE;
chcr              504 drivers/staging/comedi/drivers/mite.c 		chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
chcr              507 drivers/staging/comedi/drivers/mite.c 		chcr |= CHCR_DEV_TO_MEM;
chcr              509 drivers/staging/comedi/drivers/mite.c 	writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel));
chcr               29 include/linux/sh_dma.h 	u32		chcr;
chcr               31 sound/soc/sh/rcar/dma.c 	u32			chcr;
chcr              456 sound/soc/sh/rcar/dma.c 	rsnd_dmapp_write(dma, dmapp->chcr,	PDMACHCR);
chcr              471 sound/soc/sh/rcar/dma.c 	dmapp->chcr = rsnd_dmapp_get_chcr(io, mod_from, mod_to) | PDMACHCR_DE;
chcr              476 sound/soc/sh/rcar/dma.c 		dmapp->dmapp_id, &dma->src_addr, &dma->dst_addr, dmapp->chcr);