ch_ctl 576 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t ch_ctl = output_reg + 0x10; ch_ctl 577 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t ch_data = ch_ctl + 4; ch_ctl 596 drivers/gpu/drm/gma500/cdv_intel_dp.c if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { ch_ctl 598 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(ch_ctl)); ch_ctl 610 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(ch_ctl, ch_ctl 620 drivers/gpu/drm/gma500/cdv_intel_dp.c status = REG_READ(ch_ctl); ch_ctl 627 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(ch_ctl, ch_ctl 1146 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); ch_ctl 1150 drivers/gpu/drm/i915/display/intel_dp.c #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) ch_ctl 1155 drivers/gpu/drm/i915/display/intel_dp.c trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); ch_ctl 1293 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t ch_ctl, ch_data[5]; ch_ctl 1304 drivers/gpu/drm/i915/display/intel_dp.c ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); ch_ctl 1332 drivers/gpu/drm/i915/display/intel_dp.c status = intel_uncore_read_notrace(uncore, ch_ctl); ch_ctl 1338 drivers/gpu/drm/i915/display/intel_dp.c trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); ch_ctl 1342 drivers/gpu/drm/i915/display/intel_dp.c const u32 status = intel_uncore_read(uncore, ch_ctl); ch_ctl 1377 drivers/gpu/drm/i915/display/intel_dp.c intel_uncore_write(uncore, ch_ctl, send_ctl); ch_ctl 1383 drivers/gpu/drm/i915/display/intel_dp.c ch_ctl,