ch_control         15 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h 	u32 ch_control;  /* 0x40 Time Synchronization Channel Control */
ch_control        393 drivers/net/ethernet/xscale/ixp4xx_eth.c 		__raw_writel(0, &regs->channel[ch].ch_control);
ch_control        397 drivers/net/ethernet/xscale/ixp4xx_eth.c 		__raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
ch_control         59 drivers/ptp/ptp_pch.c 	u32 ch_control;
ch_control        187 drivers/ptp/ptp_pch.c 	val = ioread32(&chip->regs->ch_control);
ch_control        197 drivers/ptp/ptp_pch.c 	iowrite32(val, (&chip->regs->ch_control));