cg_sclk_dpm_ctrl_5  929 drivers/gpu/drm/radeon/sumo_dpm.c 	u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
cg_sclk_dpm_ctrl_5  934 drivers/gpu/drm/radeon/sumo_dpm.c 	cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
cg_sclk_dpm_ctrl_5  935 drivers/gpu/drm/radeon/sumo_dpm.c 	cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
cg_sclk_dpm_ctrl_5  937 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);