cg_sclk_dpm_ctrl_4  971 drivers/gpu/drm/radeon/sumo_dpm.c 	u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
cg_sclk_dpm_ctrl_4  978 drivers/gpu/drm/radeon/sumo_dpm.c 	cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
cg_sclk_dpm_ctrl_4  979 drivers/gpu/drm/radeon/sumo_dpm.c 	cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
cg_sclk_dpm_ctrl_4  981 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);