cfgcr2           1279 drivers/gpu/drm/i915/display/intel_ddi.c 	p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
cfgcr2           1280 drivers/gpu/drm/i915/display/intel_ddi.c 	p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
cfgcr2           1282 drivers/gpu/drm/i915/display/intel_ddi.c 	if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
cfgcr2           1283 drivers/gpu/drm/i915/display/intel_ddi.c 		p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
cfgcr2           12803 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
cfgcr2            954 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	i915_reg_t ctl, cfgcr1, cfgcr2;
cfgcr2            968 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
cfgcr2            974 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
cfgcr2            980 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
cfgcr2           1010 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
cfgcr2           1012 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	POSTING_READ(regs[id].cfgcr2);
cfgcr2           1072 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
cfgcr2           1363 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 ctrl1, cfgcr1, cfgcr2;
cfgcr2           1382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
cfgcr2           1393 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
cfgcr2           1490 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->cfgcr2);
cfgcr2            188 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 cfgcr1, cfgcr2;