cfgcr1_reg 3168 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t cfgcr0_reg, cfgcr1_reg; cfgcr1_reg 3172 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cfgcr1_reg = TGL_DPLL_CFGCR1(id); cfgcr1_reg 3176 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cfgcr1_reg = ICL_DPLL_CFGCR1(4); cfgcr1_reg 3179 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cfgcr1_reg = ICL_DPLL_CFGCR1(id); cfgcr1_reg 3184 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(cfgcr1_reg, hw_state->cfgcr1); cfgcr1_reg 3185 drivers/gpu/drm/i915/display/intel_dpll_mgr.c POSTING_READ(cfgcr1_reg);