cfgcr1           1318 drivers/gpu/drm/i915/display/intel_ddi.c 	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
cfgcr1           1321 drivers/gpu/drm/i915/display/intel_ddi.c 	dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
cfgcr1           1335 drivers/gpu/drm/i915/display/intel_ddi.c 	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
cfgcr1           1336 drivers/gpu/drm/i915/display/intel_ddi.c 	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
cfgcr1           1338 drivers/gpu/drm/i915/display/intel_ddi.c 	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
cfgcr1           1339 drivers/gpu/drm/i915/display/intel_ddi.c 		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
cfgcr1           12802 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
cfgcr1            954 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	i915_reg_t ctl, cfgcr1, cfgcr2;
cfgcr1            967 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
cfgcr1            973 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
cfgcr1            979 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
cfgcr1           1009 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
cfgcr1           1011 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	POSTING_READ(regs[id].cfgcr1);
cfgcr1           1071 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
cfgcr1           1363 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 ctrl1, cfgcr1, cfgcr2;
cfgcr1           1378 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
cfgcr1           1392 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
cfgcr1           1489 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->cfgcr1,
cfgcr1           2047 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		val = pll->state.hw_state.cfgcr1;
cfgcr1           2160 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
cfgcr1           2320 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 cfgcr0, cfgcr1;
cfgcr1           2331 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
cfgcr1           2341 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
cfgcr1           2440 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->cfgcr1);
cfgcr1           2575 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 cfgcr0, cfgcr1;
cfgcr1           2594 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
cfgcr1           2600 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
cfgcr1           2602 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
cfgcr1           2607 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	pll_state->cfgcr1 = cfgcr1;
cfgcr1           3125 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
cfgcr1           3129 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4));
cfgcr1           3132 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
cfgcr1           3184 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
cfgcr1           3421 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->cfgcr0, hw_state->cfgcr1,
cfgcr1            188 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 cfgcr1, cfgcr2;
cfgcr1           2846 drivers/gpu/drm/i915/i915_debugfs.c 		seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);