cfgcr0           1374 drivers/gpu/drm/i915/display/intel_ddi.c 	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
cfgcr0           1377 drivers/gpu/drm/i915/display/intel_ddi.c 	dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
cfgcr0           1518 drivers/gpu/drm/i915/display/intel_ddi.c 	if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
cfgcr0           1521 drivers/gpu/drm/i915/display/intel_ddi.c 		link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
cfgcr0           12804 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
cfgcr0           2038 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	val = pll->state.hw_state.cfgcr0;
cfgcr0           2046 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
cfgcr0           2156 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->cfgcr0 = val;
cfgcr0           2320 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 cfgcr0, cfgcr1;
cfgcr0           2323 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
cfgcr0           2328 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
cfgcr0           2340 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
cfgcr0           2348 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 cfgcr0;
cfgcr0           2350 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
cfgcr0           2354 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
cfgcr0           2357 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
cfgcr0           2360 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
cfgcr0           2364 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
cfgcr0           2367 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
cfgcr0           2370 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
cfgcr0           2374 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
cfgcr0           2378 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
cfgcr0           2385 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
cfgcr0           2439 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->cfgcr0,
cfgcr0           2575 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	u32 cfgcr0, cfgcr1;
cfgcr0           2591 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
cfgcr0           2606 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	pll_state->cfgcr0 = cfgcr0;
cfgcr0           3124 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
cfgcr0           3128 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4));
cfgcr0           3131 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
cfgcr0           3183 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
cfgcr0           3421 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->cfgcr0, hw_state->cfgcr1,
cfgcr0            191 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 cfgcr0;
cfgcr0           2845 drivers/gpu/drm/i915/i915_debugfs.c 		seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);