cfg_val          9205 drivers/net/ethernet/broadcom/tg3.c 			u32 cfg_val;
cfg_val          9211 drivers/net/ethernet/broadcom/tg3.c 			pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
cfg_val          9213 drivers/net/ethernet/broadcom/tg3.c 					       cfg_val | (1 << 15));
cfg_val          1639 drivers/parisc/sba_iommu.c 				unsigned long cfg_val;
cfg_val          1642 drivers/parisc/sba_iommu.c 				cfg_val = READ_REG(rope_cfg);
cfg_val          1643 drivers/parisc/sba_iommu.c 				cfg_val &= ~IOC_ROPE_AO;
cfg_val          1644 drivers/parisc/sba_iommu.c 				WRITE_REG(cfg_val, rope_cfg);
cfg_val          1338 drivers/pinctrl/bcm/pinctrl-bcm281xx.c 	u32 cfg_val, cfg_mask;
cfg_val          1341 drivers/pinctrl/bcm/pinctrl-bcm281xx.c 	cfg_val = 0;
cfg_val          1349 drivers/pinctrl/bcm/pinctrl-bcm281xx.c 			num_configs, &cfg_val, &cfg_mask);
cfg_val          1354 drivers/pinctrl/bcm/pinctrl-bcm281xx.c 			num_configs, &cfg_val, &cfg_mask);
cfg_val          1359 drivers/pinctrl/bcm/pinctrl-bcm281xx.c 			num_configs, &cfg_val, &cfg_mask);
cfg_val          1374 drivers/pinctrl/bcm/pinctrl-bcm281xx.c 		__func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
cfg_val          1376 drivers/pinctrl/bcm/pinctrl-bcm281xx.c 	rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
cfg_val           299 drivers/soc/xilinx/xlnx_vcu.c 	u32 cfg_val, mod, ctrl;
cfg_val           428 drivers/soc/xilinx/xlnx_vcu.c 	cfg_val = (found->res << VCU_PLL_CFG_RES_SHIFT) |
cfg_val           433 drivers/soc/xilinx/xlnx_vcu.c 	xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CFG, cfg_val);
cfg_val           351 sound/x86/intel_hdmi_audio.c 	union aud_cfg cfg_val = {.regval = 0};
cfg_val           363 sound/x86/intel_hdmi_audio.c 	cfg_val.regx.num_ch = channels - 2;
cfg_val           365 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.layout = LAYOUT0;
cfg_val           367 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.layout = LAYOUT1;
cfg_val           370 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.packet_mode = 1;
cfg_val           373 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.left_align = 1;
cfg_val           375 sound/x86/intel_hdmi_audio.c 	cfg_val.regx.val_bit = 1;
cfg_val           379 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.dp_modei = 1;
cfg_val           380 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.set = 1;
cfg_val           383 sound/x86/intel_hdmi_audio.c 	had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
cfg_val           384 sound/x86/intel_hdmi_audio.c 	intelhaddata->aud_config = cfg_val;