cfg_reg 425 arch/arm/mach-omap1/include/mach/mux.h int (*cfg_reg)(const struct pin_config *cfg); cfg_reg 445 arch/arm/mach-omap1/mux.c || !arch_mux_cfg->cfg_reg) { cfg_reg 483 arch/arm/mach-omap1/mux.c if (!mux_cfg->cfg_reg) cfg_reg 486 arch/arm/mach-omap1/mux.c return mux_cfg->cfg_reg(reg); cfg_reg 495 arch/arm/mach-omap1/mux.c arch_mux_cfg.cfg_reg = omap1_cfg_reg; cfg_reg 501 arch/arm/mach-omap1/mux.c arch_mux_cfg.cfg_reg = omap1_cfg_reg; cfg_reg 65 arch/sparc/kernel/sbus.c unsigned long cfg_reg; cfg_reg 77 arch/sparc/kernel/sbus.c cfg_reg = iommu->write_complete_reg; cfg_reg 80 arch/sparc/kernel/sbus.c cfg_reg += 0x20UL; cfg_reg 83 arch/sparc/kernel/sbus.c cfg_reg += 0x28UL; cfg_reg 86 arch/sparc/kernel/sbus.c cfg_reg += 0x30UL; cfg_reg 89 arch/sparc/kernel/sbus.c cfg_reg += 0x38UL; cfg_reg 92 arch/sparc/kernel/sbus.c cfg_reg += 0x40UL; cfg_reg 95 arch/sparc/kernel/sbus.c cfg_reg += 0x48UL; cfg_reg 98 arch/sparc/kernel/sbus.c cfg_reg += 0x50UL; cfg_reg 105 arch/sparc/kernel/sbus.c val = upa_readq(cfg_reg); cfg_reg 121 arch/sparc/kernel/sbus.c upa_writeq(val, cfg_reg); cfg_reg 32 drivers/clk/clk-lochnagar.c u16 cfg_reg; cfg_reg 87 drivers/clk/clk-lochnagar.c .cfg_reg = LOCHNAGAR1_##REG, \ cfg_reg 96 drivers/clk/clk-lochnagar.c .cfg_reg = LOCHNAGAR2_##ID##_CTRL, \ cfg_reg 152 drivers/clk/clk-lochnagar.c ret = regmap_update_bits(regmap, lclk->cfg_reg, cfg_reg 168 drivers/clk/clk-lochnagar.c ret = regmap_update_bits(regmap, lclk->cfg_reg, lclk->ena_mask, 0); cfg_reg 134 drivers/clk/spear/clk-vco-pll.c p = readl_relaxed(pll->vco->cfg_reg); cfg_reg 157 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(pll->vco->cfg_reg); cfg_reg 160 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, pll->vco->cfg_reg); cfg_reg 204 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->cfg_reg); cfg_reg 249 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(vco->cfg_reg); cfg_reg 261 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, vco->cfg_reg); cfg_reg 278 drivers/clk/spear/clk-vco-pll.c *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, cfg_reg 288 drivers/clk/spear/clk-vco-pll.c if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || cfg_reg 304 drivers/clk/spear/clk-vco-pll.c vco->cfg_reg = cfg_reg; cfg_reg 96 drivers/clk/spear/clk.h void __iomem *cfg_reg; cfg_reg 126 drivers/clk/spear/clk.h *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, cfg_reg 488 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *cfg_reg, cfg_reg 504 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(cfg_reg, CU_INPUT0_SIZE, cfg_reg 506 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(cfg_reg, CU_INPUT0_OFFSET, cfg_reg 508 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(cfg_reg, CU_INPUT0_CONTROL, ctrl); cfg_reg 516 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *id_reg, *cfg_reg; cfg_reg 521 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c cfg_reg = reg + index * CU_PER_INPUT_REGS; cfg_reg 523 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c compiz_enable_input(id_reg, cfg_reg, cfg_reg 528 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(cfg_reg, CU_INPUT0_CONTROL, 0); cfg_reg 884 drivers/misc/habanalabs/goya/goya.c static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg, cfg_reg 892 drivers/misc/habanalabs/goya/goya.c WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); cfg_reg 338 drivers/mmc/host/atmel-mci.c u32 cfg_reg; cfg_reg 1252 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_CFG, host->cfg_reg); cfg_reg 1400 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_CFG, host->cfg_reg); cfg_reg 1452 drivers/mmc/host/atmel-mci.c host->cfg_reg |= ATMCI_CFG_HSMODE; cfg_reg 1454 drivers/mmc/host/atmel-mci.c host->cfg_reg &= ~ATMCI_CFG_HSMODE; cfg_reg 1460 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_CFG, host->cfg_reg); cfg_reg 1568 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_CFG, host->cfg_reg); cfg_reg 1669 drivers/mmc/host/atmel-mci.c atmci_writel(host, ATMCI_CFG, host->cfg_reg); cfg_reg 634 drivers/net/ethernet/altera/altera_tse_main.c u32 cfg_reg = ioread32(&priv->mac_dev->command_config); cfg_reg 640 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg |= MAC_CMDCFG_HD_ENA; cfg_reg 642 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg &= ~MAC_CMDCFG_HD_ENA; cfg_reg 655 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg |= MAC_CMDCFG_ETH_SPEED; cfg_reg 656 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg &= ~MAC_CMDCFG_ENA_10; cfg_reg 659 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; cfg_reg 660 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg &= ~MAC_CMDCFG_ENA_10; cfg_reg 663 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; cfg_reg 664 drivers/net/ethernet/altera/altera_tse_main.c cfg_reg |= MAC_CMDCFG_ENA_10; cfg_reg 674 drivers/net/ethernet/altera/altera_tse_main.c iowrite32(cfg_reg, &priv->mac_dev->command_config); cfg_reg 1983 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c int cfg_reg; cfg_reg 1989 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; cfg_reg 1991 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cfg_reg = bp->link_params.req_fc_auto_adv; cfg_reg 1993 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == cfg_reg 1995 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == cfg_reg 954 drivers/net/ethernet/freescale/fman/fman.c u32 cfg_reg = 0; cfg_reg 961 drivers/net/ethernet/freescale/fman/fman.c cfg_reg = QMI_CFG_EN_COUNTERS; cfg_reg 964 drivers/net/ethernet/freescale/fman/fman.c cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh; cfg_reg 967 drivers/net/ethernet/freescale/fman/fman.c iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN, cfg_reg 146 drivers/net/ethernet/hisilicon/hns_mdio.c u32 cfg_reg, u32 set_val, cfg_reg 153 drivers/net/ethernet/hisilicon/hns_mdio.c regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val); cfg_reg 668 drivers/net/wireless/intel/iwlwifi/fw/file.h __le32 cfg_reg; cfg_reg 1446 drivers/net/wireless/intel/iwlwifi/iwl-drv.c dest_tlv->base_reg = pieces->dbg_dest_tlv->cfg_reg; cfg_reg 3185 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 base, end, cfg_reg, monitor_len; cfg_reg 3188 drivers/net/wireless/intel/iwlwifi/pcie/trans.c cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); cfg_reg 3189 drivers/net/wireless/intel/iwlwifi/pcie/trans.c cfg_reg = iwl_read_prph(trans, cfg_reg); cfg_reg 3190 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << cfg_reg 3196 drivers/net/wireless/intel/iwlwifi/pcie/trans.c (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> cfg_reg 440 drivers/pinctrl/samsung/pinctrl-samsung.c u32 cfg_value, cfg_reg; cfg_reg 452 drivers/pinctrl/samsung/pinctrl-samsung.c cfg_reg = type->reg_offset[cfg_type]; cfg_reg 458 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg_base + cfg_reg); cfg_reg 464 drivers/pinctrl/samsung/pinctrl-samsung.c writel(data, reg_base + cfg_reg); cfg_reg 731 drivers/pinctrl/sh-pfc/core.c const struct pinmux_cfg_reg *cfg_reg) cfg_reg 735 drivers/pinctrl/sh-pfc/core.c if (cfg_reg->field_width) { cfg_reg 740 drivers/pinctrl/sh-pfc/core.c for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) { cfg_reg 741 drivers/pinctrl/sh-pfc/core.c if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) { cfg_reg 743 drivers/pinctrl/sh-pfc/core.c drvname, cfg_reg->reg, rw, rw + fw - 1); cfg_reg 750 drivers/pinctrl/sh-pfc/core.c if (rw != cfg_reg->reg_width) { cfg_reg 752 drivers/pinctrl/sh-pfc/core.c drvname, cfg_reg->reg, rw, cfg_reg->reg_width); cfg_reg 756 drivers/pinctrl/sh-pfc/core.c if (n != cfg_reg->nr_enum_ids) { cfg_reg 758 drivers/pinctrl/sh-pfc/core.c drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n); cfg_reg 738 drivers/scsi/gdth.h u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/