cfg_4              72 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c 	u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
cfg_4              97 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c 		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);