cfg56             366 arch/mips/pci/pci-octeon.c 	union cvmx_pci_cfg56 cfg56;
cfg56             532 arch/mips/pci/pci-octeon.c 	cfg56.u32 = 0;
cfg56             533 arch/mips/pci/pci-octeon.c 	cfg56.s.pxcid = 7;	/* RO - PCI-X Capability ID */
cfg56             534 arch/mips/pci/pci-octeon.c 	cfg56.s.ncp = 0xe8;	/* RO - Next Capability Pointer */
cfg56             535 arch/mips/pci/pci-octeon.c 	cfg56.s.dpere = 1;	/* Data Parity Error Recovery Enable */
cfg56             536 arch/mips/pci/pci-octeon.c 	cfg56.s.roe = 1;	/* Relaxed Ordering Enable */
cfg56             537 arch/mips/pci/pci-octeon.c 	cfg56.s.mmbc = 1;	/* Maximum Memory Byte Count
cfg56             539 arch/mips/pci/pci-octeon.c 	cfg56.s.most = 3;	/* Maximum outstanding Split transactions [0=1
cfg56             542 arch/mips/pci/pci-octeon.c 	octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);