cfg1 85 arch/mips/lasat/lasat_board.c unsigned long cfg0, cfg1; cfg1 114 arch/mips/lasat/lasat_board.c cfg1 = lasat_board_info.li_eeprom_info.cfg[1]; cfg1 204 arch/mips/lasat/lasat_board.c switch (LASAT_W1_FLASHSIZE(cfg1)) { cfg1 21 arch/sparc/include/asm/sbi.h /* 0x0014 */ u32 cfg1; /* Slot1 config reg */ cfg1 53 drivers/clk/zte/clk-zx296702.c { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 }, cfg1 54 drivers/clk/zte/clk-zx296702.c { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa }, cfg1 55 drivers/clk/zte/clk-zx296702.c { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 }, cfg1 56 drivers/clk/zte/clk-zx296702.c { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 }, cfg1 57 drivers/clk/zte/clk-zx296702.c { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa }, cfg1 58 drivers/clk/zte/clk-zx296702.c { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 }, cfg1 58 drivers/clk/zte/clk.c if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) cfg1 101 drivers/clk/zte/clk.c writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); cfg1 17 drivers/clk/zte/clk.h u32 cfg1; cfg1 34 drivers/clk/zte/clk.h .cfg1 = _cfg1, \ cfg1 421 drivers/gpu/drm/exynos/exynos_drm_fimc.c u32 cfg1, cfg2; cfg1 425 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); cfg1 426 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | cfg1 435 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; cfg1 437 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; cfg1 442 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; cfg1 444 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; cfg1 447 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | cfg1 450 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; cfg1 452 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; cfg1 455 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | cfg1 459 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; cfg1 461 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; cfg1 465 drivers/gpu/drm/exynos/exynos_drm_fimc.c fimc_write(ctx, cfg1, EXYNOS_MSCTRL); cfg1 1013 drivers/gpu/drm/exynos/exynos_drm_fimc.c u32 cfg0, cfg1; cfg1 1038 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL); cfg1 1039 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK; cfg1 1040 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE | cfg1 1043 drivers/gpu/drm/exynos/exynos_drm_fimc.c fimc_write(ctx, cfg1, EXYNOS_CISCCTRL); cfg1 264 drivers/gpu/drm/i915/display/intel_dsi_vbt.c u16 cfg0, cfg1; cfg1 302 drivers/gpu/drm/i915/display/intel_dsi_vbt.c cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); cfg1 305 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_write(dev_priv, port, cfg1, 0); cfg1 204 drivers/gpu/drm/nouveau/dispnv04/arb.c uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); cfg1 226 drivers/gpu/drm/nouveau/dispnv04/arb.c sim_data.mem_latency = cfg1 & 0xf; cfg1 227 drivers/gpu/drm/nouveau/dispnv04/arb.c sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); cfg1 1553 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000)); cfg1 1554 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (tmp && tmp != cfg1) { cfg1 1558 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c tmp = cfg1; cfg1 233 drivers/iio/adc/imx7d_adc.c u32 cfg1 = 0; cfg1 240 drivers/iio/adc/imx7d_adc.c cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN | cfg1 250 drivers/iio/adc/imx7d_adc.c cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel); cfg1 267 drivers/iio/adc/imx7d_adc.c writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel); cfg1 360 drivers/media/platform/atmel/atmel-isi.c u32 ctrl, cfg1; cfg1 362 drivers/media/platform/atmel/atmel-isi.c cfg1 = isi_readl(isi, ISI_CFG1); cfg1 387 drivers/media/platform/atmel/atmel-isi.c cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK; cfg1 389 drivers/media/platform/atmel/atmel-isi.c cfg1 |= isi->pdata.frate | ISI_CFG1_DISCR; cfg1 398 drivers/media/platform/atmel/atmel-isi.c isi_writel(isi, ISI_CFG1, cfg1); cfg1 760 drivers/media/platform/atmel/atmel-isi.c u32 cfg1 = 0; cfg1 764 drivers/media/platform/atmel/atmel-isi.c cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW; cfg1 766 drivers/media/platform/atmel/atmel-isi.c cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW; cfg1 768 drivers/media/platform/atmel/atmel-isi.c cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING; cfg1 770 drivers/media/platform/atmel/atmel-isi.c cfg1 |= ISI_CFG1_EMB_SYNC; cfg1 772 drivers/media/platform/atmel/atmel-isi.c cfg1 |= ISI_CFG1_FULL_MODE; cfg1 774 drivers/media/platform/atmel/atmel-isi.c cfg1 |= ISI_CFG1_THMASK_BEATS_16; cfg1 780 drivers/media/platform/atmel/atmel-isi.c isi_writel(isi, ISI_CFG1, cfg1); cfg1 301 drivers/mtd/nand/raw/qcom_nandc.c __le32 cfg1; cfg1 449 drivers/mtd/nand/raw/qcom_nandc.c u32 cfg0, cfg1; cfg1 619 drivers/mtd/nand/raw/qcom_nandc.c return ®s->cfg1; cfg1 683 drivers/mtd/nand/raw/qcom_nandc.c u32 cmd, cfg0, cfg1, ecc_bch_cfg; cfg1 698 drivers/mtd/nand/raw/qcom_nandc.c cfg1 = host->cfg1; cfg1 704 drivers/mtd/nand/raw/qcom_nandc.c cfg1 = host->cfg1_raw; cfg1 710 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1); cfg1 2581 drivers/mtd/nand/raw/qcom_nandc.c host->cfg1 = 7 << NAND_RECOVERY_CYCLES cfg1 2620 drivers/mtd/nand/raw/qcom_nandc.c host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, cfg1 819 drivers/net/ethernet/agere/et131x.c ¯egs->cfg1); cfg1 861 drivers/net/ethernet/agere/et131x.c writel(0, ¯egs->cfg1); cfg1 869 drivers/net/ethernet/agere/et131x.c u32 cfg1; cfg1 875 drivers/net/ethernet/agere/et131x.c cfg1 = readl(&mac->cfg1); cfg1 889 drivers/net/ethernet/agere/et131x.c cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE | cfg1 892 drivers/net/ethernet/agere/et131x.c cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW); cfg1 894 drivers/net/ethernet/agere/et131x.c cfg1 |= ET_MAC_CFG1_RX_FLOW; cfg1 895 drivers/net/ethernet/agere/et131x.c writel(cfg1, &mac->cfg1); cfg1 921 drivers/net/ethernet/agere/et131x.c cfg1 = readl(&mac->cfg1); cfg1 922 drivers/net/ethernet/agere/et131x.c } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100); cfg1 927 drivers/net/ethernet/agere/et131x.c cfg1); cfg1 1693 drivers/net/ethernet/agere/et131x.c writel(reg, &adapter->regs->mac.cfg1); cfg1 1700 drivers/net/ethernet/agere/et131x.c writel(reg, &adapter->regs->mac.cfg1); cfg1 1701 drivers/net/ethernet/agere/et131x.c writel(0, &adapter->regs->mac.cfg1); cfg1 1048 drivers/net/ethernet/agere/et131x.h u32 cfg1; /* 0x5000 */ cfg1 5135 drivers/net/ethernet/realtek/r8169_main.c u8 cfg1; cfg1 5147 drivers/net/ethernet/realtek/r8169_main.c cfg1 = RTL_R8(tp, Config1); cfg1 5148 drivers/net/ethernet/realtek/r8169_main.c if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) cfg1 5149 drivers/net/ethernet/realtek/r8169_main.c RTL_W8(tp, Config1, cfg1 & ~LEDS0); cfg1 905 drivers/net/ethernet/smsc/smc91x.c int bmcr, cfg1; cfg1 910 drivers/net/ethernet/smsc/smc91x.c cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); cfg1 911 drivers/net/ethernet/smsc/smc91x.c cfg1 |= PHY_CFG1_LNKDIS; cfg1 912 drivers/net/ethernet/smsc/smc91x.c smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); cfg1 187 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c u32 cfg0, cfg1; cfg1 191 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c cfg1 = 0x00011414; cfg1 194 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c cfg1 = 0x00021414; cfg1 197 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_wr(dev, MT_TX_SW_CFG1, cfg1); cfg1 327 drivers/pci/controller/pcie-altera.c u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1; cfg1 331 drivers/pci/controller/pcie-altera.c cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1; cfg1 333 drivers/pci/controller/pcie-altera.c cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1; cfg1 607 drivers/pci/switch/switchtec.c set_fw_info_part(&info, &fi->cfg1); cfg1 365 drivers/perf/fsl_imx8_ddr_perf.c int cfg1 = event->attr.config1; cfg1 378 drivers/perf/fsl_imx8_ddr_perf.c cfg1 ^= AXI_MASKING_REVERT; cfg1 379 drivers/perf/fsl_imx8_ddr_perf.c writel(cfg1, pmu->base + COUNTER_DPCR1); cfg1 323 drivers/pinctrl/intel/pinctrl-intel.c u32 cfg0, cfg1, mode; cfg1 333 drivers/pinctrl/intel/pinctrl-intel.c cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); cfg1 341 drivers/pinctrl/intel/pinctrl-intel.c seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); cfg1 2180 drivers/scsi/qla1280.c uint16_t hwrev, cfg1, cdma_conf, ddma_conf; cfg1 2184 drivers/scsi/qla1280.c cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); cfg1 2190 drivers/scsi/qla1280.c cfg1 |= nv->isp_config.fifo_threshold << 4; cfg1 2192 drivers/scsi/qla1280.c cfg1 |= nv->isp_config.burst_enable << 2; cfg1 2193 drivers/scsi/qla1280.c WRT_REG_WORD(®->cfg_1, cfg1); cfg1 2198 drivers/scsi/qla1280.c uint16_t cfg1, term; cfg1 2201 drivers/scsi/qla1280.c cfg1 = nv->isp_config.fifo_threshold << 4; cfg1 2202 drivers/scsi/qla1280.c cfg1 |= nv->isp_config.burst_enable << 2; cfg1 2205 drivers/scsi/qla1280.c cfg1 |= BIT_13; cfg1 2206 drivers/scsi/qla1280.c WRT_REG_WORD(®->cfg_1, cfg1); cfg1 382 drivers/soc/qcom/qcom-geni-se.c u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; cfg1 411 drivers/soc/qcom/qcom-geni-se.c cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); cfg1 415 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); cfg1 419 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); cfg1 409 drivers/spi/spi-stm32.c u32 cfg1, max_bpw; cfg1 419 drivers/spi/spi-stm32.c cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); cfg1 420 drivers/spi/spi-stm32.c max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >> cfg1 108 drivers/staging/comedi/drivers/ni_at_ao.c unsigned short cfg1; cfg1 120 drivers/staging/comedi/drivers/ni_at_ao.c devpriv->cfg1 |= ATAO_CFG1_GRP2WR; cfg1 122 drivers/staging/comedi/drivers/ni_at_ao.c devpriv->cfg1 &= ~ATAO_CFG1_GRP2WR; cfg1 123 drivers/staging/comedi/drivers/ni_at_ao.c outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); cfg1 271 drivers/staging/comedi/drivers/ni_at_ao.c devpriv->cfg1 = 0; cfg1 272 drivers/staging/comedi/drivers/ni_at_ao.c outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); cfg1 387 drivers/video/fbdev/nvidia/nv_hw.c unsigned int MClk, NVClk, cfg1; cfg1 391 drivers/video/fbdev/nvidia/nv_hw.c cfg1 = NV_RD32(par->PFB, 0x00000204); cfg1 397 drivers/video/fbdev/nvidia/nv_hw.c sim_data.mem_latency = (char)cfg1 & 0x0F; cfg1 400 drivers/video/fbdev/nvidia/nv_hw.c (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); cfg1 626 drivers/video/fbdev/nvidia/nv_hw.c unsigned int MClk, NVClk, cfg1; cfg1 630 drivers/video/fbdev/nvidia/nv_hw.c cfg1 = NV_RD32(par->PFB, 0x0204); cfg1 637 drivers/video/fbdev/nvidia/nv_hw.c sim_data.mem_latency = (char)cfg1 & 0x0F; cfg1 640 drivers/video/fbdev/nvidia/nv_hw.c (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); cfg1 808 drivers/video/fbdev/riva/riva_hw.c unsigned int M, N, P, pll, MClk, NVClk, cfg1; cfg1 816 drivers/video/fbdev/riva/riva_hw.c cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); cfg1 822 drivers/video/fbdev/riva/riva_hw.c sim_data.mem_latency = (char)cfg1 & 0x0F; cfg1 824 drivers/video/fbdev/riva/riva_hw.c sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); cfg1 1071 drivers/video/fbdev/riva/riva_hw.c unsigned int M, N, P, pll, MClk, NVClk, cfg1; cfg1 1079 drivers/video/fbdev/riva/riva_hw.c cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); cfg1 1087 drivers/video/fbdev/riva/riva_hw.c sim_data.mem_latency = (char)cfg1 & 0x0F; cfg1 1089 drivers/video/fbdev/riva/riva_hw.c sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); cfg1 147 include/linux/switchtec.h struct partition_info cfg1; cfg1 712 sound/pci/als4000.c u32 cfg1 = 0; cfg1 720 sound/pci/als4000.c cfg1 |= (game_io | 1) << 16; cfg1 722 sound/pci/als4000.c cfg1 |= (opl_io | 1); cfg1 723 sound/pci/als4000.c snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA8_LEGACY_CFG1, cfg1); cfg1 112 sound/pci/au88x0/au88x0.h int cfg1; cfg1 1097 sound/pci/au88x0/au88x0_core.c dma->cfg1 = 0; cfg1 1102 sound/pci/au88x0/au88x0_core.c dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1); cfg1 1110 sound/pci/au88x0/au88x0_core.c dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); cfg1 1135 sound/pci/au88x0/au88x0_core.c hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1); cfg1 1376 sound/pci/au88x0/au88x0_core.c dma->cfg1 = 0; cfg1 1381 sound/pci/au88x0/au88x0_core.c dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1); cfg1 1388 sound/pci/au88x0/au88x0_core.c dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); cfg1 1406 sound/pci/au88x0/au88x0_core.c hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1); cfg1 1642 sound/soc/codecs/wcd9335.c u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; cfg1 1655 sound/soc/codecs/wcd9335.c cfg1 = snd_soc_component_read32(comp, cfg1 1662 sound/soc/codecs/wcd9335.c inp2_sel = (cfg1 >> 4) & cfg1 507 sound/soc/stm/stm32_i2s.c u32 cfgr, cfgr_mask, cfg1; cfg1 543 sound/soc/stm/stm32_i2s.c cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1); cfg1 546 sound/soc/stm/stm32_i2s.c I2S_CFG1_FTHVL_MASK, cfg1);