cfg0 85 arch/mips/lasat/lasat_board.c unsigned long cfg0, cfg1; cfg0 113 arch/mips/lasat/lasat_board.c cfg0 = lasat_board_info.li_eeprom_info.cfg[0]; cfg0 116 arch/mips/lasat/lasat_board.c if (LASAT_W0_DSCTYPE(cfg0) != 1) { cfg0 123 arch/mips/lasat/lasat_board.c switch (LASAT_W0_SDRAMBANKSZ(cfg0)) { cfg0 143 arch/mips/lasat/lasat_board.c switch (LASAT_W0_SDRAMBANKS(cfg0)) { cfg0 153 arch/mips/lasat/lasat_board.c switch (LASAT_W0_BUSSPEED(cfg0)) { cfg0 174 arch/mips/lasat/lasat_board.c switch (LASAT_W0_CPUCLK(cfg0)) { cfg0 224 arch/mips/lasat/lasat_board.c lasat_board_info.li_bmid = LASAT_W0_BMID(cfg0); cfg0 649 arch/mips/ralink/mt7620.c u32 cfg0; cfg0 690 arch/mips/ralink/mt7620.c cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); cfg0 692 arch/mips/ralink/mt7620.c dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; cfg0 694 arch/mips/ralink/mt7620.c dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & cfg0 20 arch/sparc/include/asm/sbi.h /* 0x0010 */ u32 cfg0; /* Slot0 config reg */ cfg0 86 drivers/clk/sirf/clk-common.c u32 cfg0 = clkc_readl(clk->regofs); cfg0 87 drivers/clk/sirf/clk-common.c u32 nf = (cfg0 & (BIT(13) - 1)) + 1; cfg0 88 drivers/clk/sirf/clk-common.c u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; cfg0 89 drivers/clk/sirf/clk-common.c u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; cfg0 53 drivers/clk/zte/clk-zx296702.c { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 }, cfg0 54 drivers/clk/zte/clk-zx296702.c { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa }, cfg0 55 drivers/clk/zte/clk-zx296702.c { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 }, cfg0 56 drivers/clk/zte/clk-zx296702.c { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 }, cfg0 57 drivers/clk/zte/clk-zx296702.c { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa }, cfg0 58 drivers/clk/zte/clk-zx296702.c { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 }, cfg0 58 drivers/clk/zte/clk.c if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) cfg0 100 drivers/clk/zte/clk.c writel_relaxed(config->cfg0, zx_pll->reg_base); cfg0 16 drivers/clk/zte/clk.h u32 cfg0; cfg0 33 drivers/clk/zte/clk.h .cfg0 = _cfg0, \ cfg0 40 drivers/edac/octeon_edac-lmc.c union cvmx_lmcx_mem_cfg0 cfg0; cfg0 44 drivers/edac/octeon_edac-lmc.c cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx)); cfg0 45 drivers/edac/octeon_edac-lmc.c if (cfg0.s.sec_err || cfg0.s.ded_err) { cfg0 54 drivers/edac/octeon_edac-lmc.c if (cfg0.s.sec_err) { cfg0 57 drivers/edac/octeon_edac-lmc.c cfg0.s.sec_err = -1; /* Done, re-arm */ cfg0 61 drivers/edac/octeon_edac-lmc.c if (cfg0.s.ded_err) { cfg0 64 drivers/edac/octeon_edac-lmc.c cfg0.s.ded_err = -1; /* Done, re-arm */ cfg0 68 drivers/edac/octeon_edac-lmc.c cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64); cfg0 238 drivers/edac/octeon_edac-lmc.c union cvmx_lmcx_mem_cfg0 cfg0; cfg0 240 drivers/edac/octeon_edac-lmc.c cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0)); cfg0 241 drivers/edac/octeon_edac-lmc.c if (!cfg0.s.ecc_ena) { cfg0 263 drivers/edac/octeon_edac-lmc.c cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc)); cfg0 264 drivers/edac/octeon_edac-lmc.c cfg0.s.intr_ded_ena = 0; /* We poll */ cfg0 265 drivers/edac/octeon_edac-lmc.c cfg0.s.intr_sec_ena = 0; cfg0 266 drivers/edac/octeon_edac-lmc.c cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64); cfg0 1013 drivers/gpu/drm/exynos/exynos_drm_fimc.c u32 cfg0, cfg1; cfg0 1025 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg0 = fimc_read(ctx, EXYNOS_MSCTRL); cfg0 1026 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; cfg0 1027 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; cfg0 1028 drivers/gpu/drm/exynos/exynos_drm_fimc.c fimc_write(ctx, cfg0, EXYNOS_MSCTRL); cfg0 1033 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT); cfg0 1034 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; cfg0 1035 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; cfg0 1046 drivers/gpu/drm/exynos/exynos_drm_fimc.c cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; cfg0 1047 drivers/gpu/drm/exynos/exynos_drm_fimc.c fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT); cfg0 264 drivers/gpu/drm/i915/display/intel_dsi_vbt.c u16 cfg0, cfg1; cfg0 301 drivers/gpu/drm/i915/display/intel_dsi_vbt.c cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); cfg0 306 drivers/gpu/drm/i915/display/intel_dsi_vbt.c vlv_iosf_sb_write(dev_priv, port, cfg0, cfg0 31 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c u32 cfg0 = nvkm_rd32(device, 0x100200); cfg0 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c if (cfg0 & 0x00000001) cfg0 300 drivers/mtd/nand/raw/qcom_nandc.c __le32 cfg0; cfg0 449 drivers/mtd/nand/raw/qcom_nandc.c u32 cfg0, cfg1; cfg0 617 drivers/mtd/nand/raw/qcom_nandc.c return ®s->cfg0; cfg0 683 drivers/mtd/nand/raw/qcom_nandc.c u32 cmd, cfg0, cfg1, ecc_bch_cfg; cfg0 695 drivers/mtd/nand/raw/qcom_nandc.c cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) | cfg0 701 drivers/mtd/nand/raw/qcom_nandc.c cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | cfg0 709 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0); cfg0 2572 drivers/mtd/nand/raw/qcom_nandc.c host->cfg0 = (cwperpage - 1) << CW_PER_PAGE cfg0 2620 drivers/mtd/nand/raw/qcom_nandc.c host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, cfg0 107 drivers/net/phy/dp83640.c int cfg0; cfg0 544 drivers/net/phy/dp83640.c u16 cfg0 = 0, ver; cfg0 547 drivers/net/phy/dp83640.c cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; cfg0 553 drivers/net/phy/dp83640.c ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); cfg0 627 drivers/net/phy/dp83640.c u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; cfg0 644 drivers/net/phy/dp83640.c tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); cfg0 649 drivers/net/phy/dp83640.c cfg0 = ext_read(master, PAGE5, PSF_CFG0); cfg0 725 drivers/net/phy/dp83640.c ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); cfg0 727 drivers/net/phy/dp83640.c ext_write(0, master, PAGE5, PSF_CFG0, cfg0); cfg0 187 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c u32 cfg0, cfg1; cfg0 190 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c cfg0 = bw ? 0x000b0c01 : 0x00101101; cfg0 193 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c cfg0 = bw ? 0x000b0b01 : 0x00101001; cfg0 196 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_wr(dev, MT_TX_SW_CFG0, cfg0); cfg0 326 drivers/pci/controller/pcie-altera.c u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0; cfg0 331 drivers/pci/controller/pcie-altera.c cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1; cfg0 333 drivers/pci/controller/pcie-altera.c cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1; cfg0 601 drivers/pci/switch/switchtec.c set_fw_info_part(&info, &fi->cfg0); cfg0 323 drivers/pinctrl/intel/pinctrl-intel.c u32 cfg0, cfg1, mode; cfg0 332 drivers/pinctrl/intel/pinctrl-intel.c cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); cfg0 335 drivers/pinctrl/intel/pinctrl-intel.c mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; cfg0 341 drivers/pinctrl/intel/pinctrl-intel.c seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); cfg0 196 drivers/scsi/dc395x.c u8 cfg0; /* Target configuration byte 0 */ cfg0 683 drivers/scsi/dc395x.c eeprom->target[id].cfg0 = cfg0 1181 drivers/scsi/dc395x.c dcb->dev_mode = eeprom->target[dcb->target_id].cfg0; cfg0 3641 drivers/scsi/dc395x.c dcb->dev_mode = eeprom->target[target].cfg0; cfg0 4133 drivers/scsi/dc395x.c eeprom->target[0].cfg0); cfg0 382 drivers/soc/qcom/qcom-geni-se.c u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; cfg0 410 drivers/soc/qcom/qcom-geni-se.c cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); cfg0 414 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); cfg0 418 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); cfg0 145 include/linux/switchtec.h } cfg0; cfg0 111 sound/pci/au88x0/au88x0.h int cfg0; cfg0 1096 sound/pci/au88x0/au88x0_core.c dma->cfg0 = 0; cfg0 1109 sound/pci/au88x0/au88x0_core.c dma->cfg0 |= 0x12000000; cfg0 1117 sound/pci/au88x0/au88x0_core.c dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1); cfg0 1124 sound/pci/au88x0/au88x0_core.c dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); cfg0 1134 sound/pci/au88x0/au88x0_core.c hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0); cfg0 1375 sound/pci/au88x0/au88x0_core.c dma->cfg0 = 0; cfg0 1387 sound/pci/au88x0/au88x0_core.c dma->cfg0 |= 0x12000000; cfg0 1394 sound/pci/au88x0/au88x0_core.c dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1); cfg0 1400 sound/pci/au88x0/au88x0_core.c dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); cfg0 1405 sound/pci/au88x0/au88x0_core.c hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0); cfg0 1642 sound/soc/codecs/wcd9335.c u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; cfg0 1653 sound/soc/codecs/wcd9335.c cfg0 = snd_soc_component_read32(comp, cfg0 1658 sound/soc/codecs/wcd9335.c inp0_sel = cfg0 & cfg0 1660 sound/soc/codecs/wcd9335.c inp1_sel = (cfg0 >> 4) &