cdv               263 drivers/gpu/drm/gma500/cdv_device.c 	pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
cdv               265 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
cdv               266 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
cdv               268 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPARB = REG_READ(DSPARB);
cdv               269 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
cdv               270 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
cdv               271 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
cdv               272 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
cdv               273 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
cdv               274 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
cdv               276 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveADPA = REG_READ(ADPA);
cdv               278 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
cdv               279 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
cdv               282 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveLVDS = REG_READ(LVDS);
cdv               284 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
cdv               286 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
cdv               287 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
cdv               288 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
cdv               290 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
cdv               292 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
cdv               293 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
cdv               316 drivers/gpu/drm/gma500/cdv_device.c 	pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
cdv               318 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
cdv               319 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
cdv               339 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
cdv               340 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
cdv               341 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
cdv               342 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
cdv               343 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
cdv               344 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
cdv               346 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
cdv               347 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(ADPA, regs->cdv.saveADPA);
cdv               350 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(LVDS, regs->cdv.saveLVDS);
cdv               351 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
cdv               352 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
cdv               354 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
cdv               355 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
cdv               356 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
cdv               357 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
cdv               359 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
cdv               361 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
cdv               362 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
cdv               419 drivers/gpu/drm/gma500/psb_drv.h 		struct cdv_state cdv;
cdv               114 drivers/net/can/cc770/cc770_platform.c 		u32 cdv = clkext / *prop;
cdv               117 drivers/net/can/cc770/cc770_platform.c 		if (cdv > 0 && cdv < 16) {
cdv               119 drivers/net/can/cc770/cc770_platform.c 			priv->clkout |= (cdv - 1) & CLKOUT_CD_MASK;
cdv               129 drivers/net/can/cc770/cc770_platform.c 					((cdv * clkext - 1) / 8000000);