cdr               410 arch/arm/mach-imx/mach-pcm037.c 	.cdr		= CDR_CBP,
cdr               137 arch/mips/include/asm/txx9/tx4939.h 	} cdr;
cdr               477 drivers/crypto/inside-secure/safexcel.c 		writel(lower_32_bits(priv->ring[i].cdr.base_dma),
cdr               479 drivers/crypto/inside-secure/safexcel.c 		writel(upper_32_bits(priv->ring[i].cdr.base_dma),
cdr               908 drivers/crypto/inside-secure/safexcel.c 		cdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].cdr);
cdr               959 drivers/crypto/inside-secure/safexcel.c 	safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
cdr              1461 drivers/crypto/inside-secure/safexcel.c 						     &priv->ring[i].cdr,
cdr               622 drivers/crypto/inside-secure/safexcel.h 	struct safexcel_desc_ring cdr;
cdr               787 drivers/crypto/inside-secure/safexcel.h 				   struct safexcel_desc_ring *cdr,
cdr               760 drivers/crypto/inside-secure/safexcel_cipher.c 		safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
cdr               398 drivers/crypto/inside-secure/safexcel_hash.c 		safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
cdr                14 drivers/crypto/inside-secure/safexcel_ring.c 				   struct safexcel_desc_ring *cdr,
cdr                17 drivers/crypto/inside-secure/safexcel_ring.c 	cdr->offset = sizeof(u32) * priv->config.cd_offset;
cdr                18 drivers/crypto/inside-secure/safexcel_ring.c 	cdr->base = dmam_alloc_coherent(priv->dev,
cdr                19 drivers/crypto/inside-secure/safexcel_ring.c 					cdr->offset * EIP197_DEFAULT_RING_SIZE,
cdr                20 drivers/crypto/inside-secure/safexcel_ring.c 					&cdr->base_dma, GFP_KERNEL);
cdr                21 drivers/crypto/inside-secure/safexcel_ring.c 	if (!cdr->base)
cdr                23 drivers/crypto/inside-secure/safexcel_ring.c 	cdr->write = cdr->base;
cdr                24 drivers/crypto/inside-secure/safexcel_ring.c 	cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
cdr                25 drivers/crypto/inside-secure/safexcel_ring.c 	cdr->read = cdr->base;
cdr               124 drivers/crypto/inside-secure/safexcel_ring.c 	cdesc = safexcel_ring_next_wptr(priv, &priv->ring[ring_id].cdr);
cdr               234 drivers/mtd/devices/docg3.c 	int i, cdr, len4;
cdr               239 drivers/mtd/devices/docg3.c 	cdr = len & 0x1;
cdr               240 drivers/mtd/devices/docg3.c 	len4 = len - cdr;
cdr               253 drivers/mtd/devices/docg3.c 	if (cdr) {
cdr               258 drivers/mtd/devices/docg3.c 		for (i = 0; i < cdr; i++) {
cdr               278 drivers/mtd/devices/docg3.c 	int i, cdr, len4;
cdr               283 drivers/mtd/devices/docg3.c 	cdr = len & 0x3;
cdr               284 drivers/mtd/devices/docg3.c 	len4 = len - cdr;
cdr               294 drivers/mtd/devices/docg3.c 	for (i = 0; i < cdr; i++) {
cdr               312 drivers/net/can/sja1000/ems_pci.c 			priv->cdr = EMS_PCI_CDR;
cdr               219 drivers/net/can/sja1000/ems_pcmcia.c 			priv->cdr = EMS_PCMCIA_CDR;
cdr               170 drivers/net/can/sja1000/f81601.c 		priv->cdr = CDR_CBP;
cdr               250 drivers/net/can/sja1000/kvaser_pci.c 	priv->cdr = KVASER_PCI_CDR;
cdr               628 drivers/net/can/sja1000/peak_pci.c 		priv->cdr = PEAK_PCI_CDR;
cdr               631 drivers/net/can/sja1000/peak_pci.c 			priv->cdr |= CDR_CLK_OFF;
cdr               562 drivers/net/can/sja1000/peak_pcmcia.c 		priv->cdr = PCC_CDR;
cdr               566 drivers/net/can/sja1000/peak_pcmcia.c 			priv->cdr |= CDR_CLK_OFF;
cdr               169 drivers/net/can/sja1000/plx_pci.c 	u8 cdr;			/* clock divider register */
cdr               704 drivers/net/can/sja1000/plx_pci.c 			priv->cdr = ci->cdr;
cdr               188 drivers/net/can/sja1000/sja1000.c 	priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);
cdr               172 drivers/net/can/sja1000/sja1000.h 	u8 cdr;			/* clock divider register */
cdr                35 drivers/net/can/sja1000/sja1000_isa.c static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
cdr                56 drivers/net/can/sja1000/sja1000_isa.c module_param_array(cdr, byte, NULL, 0444);
cdr                57 drivers/net/can/sja1000/sja1000_isa.c MODULE_PARM_DESC(cdr, "Clock divider register "
cdr               190 drivers/net/can/sja1000/sja1000_isa.c 	if (cdr[idx] != 0xff)
cdr               191 drivers/net/can/sja1000/sja1000_isa.c 		priv->cdr = cdr[idx];
cdr               192 drivers/net/can/sja1000/sja1000_isa.c 	else if (cdr[0] != 0xff)
cdr               193 drivers/net/can/sja1000/sja1000_isa.c 		priv->cdr = cdr[0];
cdr               195 drivers/net/can/sja1000/sja1000_isa.c 		priv->cdr = CDR_DEFAULT;
cdr               116 drivers/net/can/sja1000/sja1000_platform.c 	priv->cdr = pdata->cdr;
cdr               182 drivers/net/can/sja1000/sja1000_platform.c 			priv->cdr |= divider / 2 - 1;
cdr               184 drivers/net/can/sja1000/sja1000_platform.c 			priv->cdr |= CDR_CLKOUT_MASK;
cdr               186 drivers/net/can/sja1000/sja1000_platform.c 		priv->cdr |= CDR_CLK_OFF; /* default */
cdr               190 drivers/net/can/sja1000/sja1000_platform.c 		priv->cdr |= CDR_CBP; /* default */
cdr               128 drivers/net/can/sja1000/tscan1.c 	priv->cdr = CDR_CBP | CDR_CLK_OFF;
cdr                33 include/linux/can/platform/sja1000.h 	u8 cdr;		/* clock divider register */