cdp_cfg           389 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	.cdp_cfg = {
cdp_cfg           637 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 	struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
cdp_cfg          1060 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
cdp_cfg          1062 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
cdp_cfg          1064 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
cdp_cfg          1066 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			cdp_cfg->ubwc_meta_enable =
cdp_cfg          1068 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			cdp_cfg->tile_amortize_enable =
cdp_cfg          1071 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
cdp_cfg          1073 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
cdp_cfg            41 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h 	struct dpu_hw_pipe_cdp_cfg cdp_cfg;