cdm 57 arch/powerpc/platforms/52xx/lite5200.c struct mpc52xx_cdm __iomem *cdm; cdm 60 arch/powerpc/platforms/52xx/lite5200.c cdm = of_iomap(np, 0); cdm 62 arch/powerpc/platforms/52xx/lite5200.c if (!cdm) { cdm 69 arch/powerpc/platforms/52xx/lite5200.c out_8(&cdm->ext_48mhz_en, 0x00); cdm 70 arch/powerpc/platforms/52xx/lite5200.c out_8(&cdm->fd_enable, 0x01); cdm 71 arch/powerpc/platforms/52xx/lite5200.c if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ cdm 72 arch/powerpc/platforms/52xx/lite5200.c out_be16(&cdm->fd_counters, 0x0001); cdm 74 arch/powerpc/platforms/52xx/lite5200.c out_be16(&cdm->fd_counters, 0x5555); cdm 77 arch/powerpc/platforms/52xx/lite5200.c iounmap(cdm); cdm 12 arch/powerpc/platforms/52xx/lite5200_pm.c static struct mpc52xx_cdm __iomem *cdm; cdm 78 arch/powerpc/platforms/52xx/lite5200_pm.c cdm = mbar + 0x200; cdm 103 arch/powerpc/platforms/52xx/lite5200_pm.c _memcpy_fromio(&scdm, cdm, sizeof(*cdm)); cdm 139 arch/powerpc/platforms/52xx/lite5200_pm.c out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel); cdm 140 arch/powerpc/platforms/52xx/lite5200_pm.c out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel); cdm 142 arch/powerpc/platforms/52xx/lite5200_pm.c out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en); cdm 143 arch/powerpc/platforms/52xx/lite5200_pm.c out_8(&cdm->fd_enable, scdm.fd_enable); cdm 144 arch/powerpc/platforms/52xx/lite5200_pm.c out_be16(&cdm->fd_counters, scdm.fd_counters); cdm 146 arch/powerpc/platforms/52xx/lite5200_pm.c out_be32(&cdm->clk_enables, scdm.clk_enables); cdm 148 arch/powerpc/platforms/52xx/lite5200_pm.c out_8(&cdm->osc_disable, scdm.osc_disable); cdm 150 arch/powerpc/platforms/52xx/lite5200_pm.c out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1); cdm 151 arch/powerpc/platforms/52xx/lite5200_pm.c out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2); cdm 152 arch/powerpc/platforms/52xx/lite5200_pm.c out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3); cdm 153 arch/powerpc/platforms/52xx/lite5200_pm.c out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6); cdm 19 arch/powerpc/platforms/52xx/mpc52xx_pm.c static struct mpc52xx_cdm __iomem *cdm; cdm 88 arch/powerpc/platforms/52xx/mpc52xx_pm.c cdm = mbar + 0x200; cdm 138 arch/powerpc/platforms/52xx/mpc52xx_pm.c out_8(&cdm->ccs_sleep_enable, 1); cdm 139 arch/powerpc/platforms/52xx/mpc52xx_pm.c out_8(&cdm->osc_sleep_enable, 1); cdm 140 arch/powerpc/platforms/52xx/mpc52xx_pm.c out_8(&cdm->ccs_qreq_test, 1); cdm 143 arch/powerpc/platforms/52xx/mpc52xx_pm.c clk_enables = in_be32(&cdm->clk_enables); cdm 144 arch/powerpc/platforms/52xx/mpc52xx_pm.c out_be32(&cdm->clk_enables, clk_enables & 0x00088000); cdm 160 arch/powerpc/platforms/52xx/mpc52xx_pm.c mpc52xx_deep_sleep(sram, sdram, cdm, intr); cdm 171 arch/powerpc/platforms/52xx/mpc52xx_pm.c out_be32(&cdm->clk_enables, clk_enables); cdm 172 arch/powerpc/platforms/52xx/mpc52xx_pm.c out_8(&cdm->ccs_sleep_enable, 0); cdm 173 arch/powerpc/platforms/52xx/mpc52xx_pm.c out_8(&cdm->osc_sleep_enable, 0); cdm 528 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .cdm = { cdm 619 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .cdm = { cdm 721 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .cdm = { cdm 94 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h struct mdp5_sub_block cdm; cdm 44 drivers/net/can/mscan/mpc5xxx_can.c struct mpc52xx_cdm __iomem *cdm; cdm 77 drivers/net/can/mscan/mpc5xxx_can.c cdm = of_iomap(np_cdm, 0); cdm 78 drivers/net/can/mscan/mpc5xxx_can.c if (!cdm) { cdm 84 drivers/net/can/mscan/mpc5xxx_can.c if (in_8(&cdm->ipb_clk_sel) & 0x1) cdm 86 drivers/net/can/mscan/mpc5xxx_can.c val = in_be32(&cdm->rstcfg); cdm 92 drivers/net/can/mscan/mpc5xxx_can.c iounmap(cdm); cdm 108 drivers/spi/spi-ppc4xx.c u8 cdm; cdm 171 drivers/spi/spi-ppc4xx.c u8 cdm = 0; cdm 203 drivers/spi/spi-ppc4xx.c cdm = min(scr, 0xff); cdm 205 drivers/spi/spi-ppc4xx.c dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); cdm 207 drivers/spi/spi-ppc4xx.c if (in_8(&hw->regs->cdm) != cdm) cdm 208 drivers/spi/spi-ppc4xx.c out_8(&hw->regs->cdm, cdm);