cdesc 64 drivers/clk/ti/clk-dra7-atl.c struct dra7_atl_desc *cdesc; cdesc 82 drivers/clk/ti/clk-dra7-atl.c struct dra7_atl_desc *cdesc = to_atl_desc(hw); cdesc 84 drivers/clk/ti/clk-dra7-atl.c if (!cdesc->probed) cdesc 87 drivers/clk/ti/clk-dra7-atl.c if (unlikely(!cdesc->valid)) cdesc 88 drivers/clk/ti/clk-dra7-atl.c dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n", cdesc 89 drivers/clk/ti/clk-dra7-atl.c cdesc->id); cdesc 90 drivers/clk/ti/clk-dra7-atl.c pm_runtime_get_sync(cdesc->cinfo->dev); cdesc 92 drivers/clk/ti/clk-dra7-atl.c atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id), cdesc 93 drivers/clk/ti/clk-dra7-atl.c cdesc->divider - 1); cdesc 94 drivers/clk/ti/clk-dra7-atl.c atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN); cdesc 97 drivers/clk/ti/clk-dra7-atl.c cdesc->enabled = true; cdesc 104 drivers/clk/ti/clk-dra7-atl.c struct dra7_atl_desc *cdesc = to_atl_desc(hw); cdesc 106 drivers/clk/ti/clk-dra7-atl.c if (!cdesc->probed) cdesc 109 drivers/clk/ti/clk-dra7-atl.c atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0); cdesc 110 drivers/clk/ti/clk-dra7-atl.c pm_runtime_put_sync(cdesc->cinfo->dev); cdesc 113 drivers/clk/ti/clk-dra7-atl.c cdesc->enabled = false; cdesc 118 drivers/clk/ti/clk-dra7-atl.c struct dra7_atl_desc *cdesc = to_atl_desc(hw); cdesc 120 drivers/clk/ti/clk-dra7-atl.c return cdesc->enabled; cdesc 126 drivers/clk/ti/clk-dra7-atl.c struct dra7_atl_desc *cdesc = to_atl_desc(hw); cdesc 128 drivers/clk/ti/clk-dra7-atl.c return parent_rate / cdesc->divider; cdesc 146 drivers/clk/ti/clk-dra7-atl.c struct dra7_atl_desc *cdesc; cdesc 152 drivers/clk/ti/clk-dra7-atl.c cdesc = to_atl_desc(hw); cdesc 157 drivers/clk/ti/clk-dra7-atl.c cdesc->divider = divider + 1; cdesc 244 drivers/clk/ti/clk-dra7-atl.c struct dra7_atl_desc *cdesc; cdesc 265 drivers/clk/ti/clk-dra7-atl.c cdesc = to_atl_desc(__clk_get_hw(clk)); cdesc 266 drivers/clk/ti/clk-dra7-atl.c cdesc->cinfo = cinfo; cdesc 267 drivers/clk/ti/clk-dra7-atl.c cdesc->id = i; cdesc 274 drivers/clk/ti/clk-dra7-atl.c &cdesc->bws); cdesc 276 drivers/clk/ti/clk-dra7-atl.c &cdesc->aws); cdesc 278 drivers/clk/ti/clk-dra7-atl.c cdesc->valid = true; cdesc 280 drivers/clk/ti/clk-dra7-atl.c cdesc->bws); cdesc 282 drivers/clk/ti/clk-dra7-atl.c cdesc->aws); cdesc 287 drivers/clk/ti/clk-dra7-atl.c cdesc->probed = true; cdesc 292 drivers/clk/ti/clk-dra7-atl.c if (cdesc->enabled) cdesc 773 drivers/crypto/inside-secure/safexcel.c int ret, nreq = 0, cdesc = 0, rdesc = 0, commands, results; cdesc 811 drivers/crypto/inside-secure/safexcel.c cdesc += commands; cdesc 843 drivers/crypto/inside-secure/safexcel.c writel((cdesc * priv->config.cd_offset) << 2, cdesc 904 drivers/crypto/inside-secure/safexcel.c struct safexcel_command_desc *cdesc; cdesc 908 drivers/crypto/inside-secure/safexcel.c cdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].cdr); cdesc 909 drivers/crypto/inside-secure/safexcel.c if (IS_ERR(cdesc)) { cdesc 914 drivers/crypto/inside-secure/safexcel.c } while (!cdesc->last_seg); cdesc 932 drivers/crypto/inside-secure/safexcel.c struct safexcel_command_desc *cdesc; cdesc 937 drivers/crypto/inside-secure/safexcel.c cdesc = safexcel_add_cdesc(priv, ring, true, true, 0, 0, 0, ctxr_dma); cdesc 938 drivers/crypto/inside-secure/safexcel.c if (IS_ERR(cdesc)) cdesc 939 drivers/crypto/inside-secure/safexcel.c return PTR_ERR(cdesc); cdesc 941 drivers/crypto/inside-secure/safexcel.c cdesc->control_data.type = EIP197_TYPE_EXTENDED; cdesc 942 drivers/crypto/inside-secure/safexcel.c cdesc->control_data.options = 0; cdesc 943 drivers/crypto/inside-secure/safexcel.c cdesc->control_data.refresh = 0; cdesc 944 drivers/crypto/inside-secure/safexcel.c cdesc->control_data.control0 = CONTEXT_CONTROL_INV_TR; cdesc 69 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_command_desc *cdesc) cdesc 74 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.options |= EIP197_OPTION_4_TOKEN_IV_CMD; cdesc 77 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.token[0] = ctx->nonce; cdesc 79 drivers/crypto/inside-secure/safexcel_cipher.c memcpy(&cdesc->control_data.token[1], iv, 8); cdesc 81 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.token[3] = cpu_to_be32(1); cdesc 85 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.options |= EIP197_OPTION_4_TOKEN_IV_CMD; cdesc 88 drivers/crypto/inside-secure/safexcel_cipher.c memcpy(&cdesc->control_data.token[0], iv, 12); cdesc 90 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.token[3] = cpu_to_be32(1); cdesc 94 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.options |= EIP197_OPTION_4_TOKEN_IV_CMD; cdesc 97 drivers/crypto/inside-secure/safexcel_cipher.c memcpy(&cdesc->control_data.token[0], iv, 15 - iv[0]); cdesc 99 drivers/crypto/inside-secure/safexcel_cipher.c memset((u8 *)&cdesc->control_data.token[0] + 15 - iv[0], cdesc 109 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.options |= EIP197_OPTION_2_TOKEN_IV_CMD; cdesc 113 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.options |= EIP197_OPTION_2_TOKEN_IV_CMD; cdesc 117 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.options |= EIP197_OPTION_4_TOKEN_IV_CMD; cdesc 120 drivers/crypto/inside-secure/safexcel_cipher.c memcpy(cdesc->control_data.token, iv, block_sz); cdesc 125 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_command_desc *cdesc, cdesc 130 drivers/crypto/inside-secure/safexcel_cipher.c safexcel_cipher_token(ctx, iv, cdesc); cdesc 133 drivers/crypto/inside-secure/safexcel_cipher.c token = (struct safexcel_token *)(cdesc->control_data.token + 4); cdesc 145 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_command_desc *cdesc, cdesc 151 drivers/crypto/inside-secure/safexcel_cipher.c safexcel_cipher_token(ctx, iv, cdesc); cdesc 155 drivers/crypto/inside-secure/safexcel_cipher.c token = (struct safexcel_token *)(cdesc->control_data.token + cdesc 168 drivers/crypto/inside-secure/safexcel_cipher.c token = (struct safexcel_token *)(cdesc->control_data.token + cdesc 410 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_command_desc *cdesc) cdesc 415 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control1 = ctx->mode; cdesc 421 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 = cdesc 428 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 = cdesc 435 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 |= cdesc 441 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 |= cdesc 447 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 = cdesc 452 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 = cdesc 459 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 |= cdesc 462 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 |= cdesc 467 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 |= cdesc 471 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 |= cdesc 475 drivers/crypto/inside-secure/safexcel_cipher.c cdesc->control_data.control0 |= cdesc 559 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_command_desc *cdesc; cdesc 652 drivers/crypto/inside-secure/safexcel_cipher.c cdesc = safexcel_add_cdesc(priv, ring, !n_cdesc, cdesc 656 drivers/crypto/inside-secure/safexcel_cipher.c if (IS_ERR(cdesc)) { cdesc 658 drivers/crypto/inside-secure/safexcel_cipher.c ret = PTR_ERR(cdesc); cdesc 664 drivers/crypto/inside-secure/safexcel_cipher.c first_cdesc = cdesc; cdesc 59 drivers/crypto/inside-secure/safexcel_hash.c static void safexcel_hash_token(struct safexcel_command_desc *cdesc, cdesc 63 drivers/crypto/inside-secure/safexcel_hash.c (struct safexcel_token *)cdesc->control_data.token; cdesc 80 drivers/crypto/inside-secure/safexcel_hash.c struct safexcel_command_desc *cdesc) cdesc 85 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control0 |= ctx->alg; cdesc 95 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control0 |= cdesc 101 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control0 |= cdesc 138 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control0 |= cdesc 144 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control0 |= cdesc 146 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control1 |= cdesc 160 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control0 |= cdesc 166 drivers/crypto/inside-secure/safexcel_hash.c cdesc->control_data.control0 |= cdesc 261 drivers/crypto/inside-secure/safexcel_hash.c struct safexcel_command_desc *cdesc, *first_cdesc = NULL; cdesc 343 drivers/crypto/inside-secure/safexcel_hash.c cdesc = safexcel_add_cdesc(priv, ring, !n_cdesc, cdesc 347 drivers/crypto/inside-secure/safexcel_hash.c if (IS_ERR(cdesc)) { cdesc 348 drivers/crypto/inside-secure/safexcel_hash.c ret = PTR_ERR(cdesc); cdesc 354 drivers/crypto/inside-secure/safexcel_hash.c first_cdesc = cdesc; cdesc 121 drivers/crypto/inside-secure/safexcel_ring.c struct safexcel_command_desc *cdesc; cdesc 124 drivers/crypto/inside-secure/safexcel_ring.c cdesc = safexcel_ring_next_wptr(priv, &priv->ring[ring_id].cdr); cdesc 125 drivers/crypto/inside-secure/safexcel_ring.c if (IS_ERR(cdesc)) cdesc 126 drivers/crypto/inside-secure/safexcel_ring.c return cdesc; cdesc 128 drivers/crypto/inside-secure/safexcel_ring.c memset(cdesc, 0, sizeof(struct safexcel_command_desc)); cdesc 130 drivers/crypto/inside-secure/safexcel_ring.c cdesc->first_seg = first; cdesc 131 drivers/crypto/inside-secure/safexcel_ring.c cdesc->last_seg = last; cdesc 132 drivers/crypto/inside-secure/safexcel_ring.c cdesc->particle_size = data_len; cdesc 133 drivers/crypto/inside-secure/safexcel_ring.c cdesc->data_lo = lower_32_bits(data); cdesc 134 drivers/crypto/inside-secure/safexcel_ring.c cdesc->data_hi = upper_32_bits(data); cdesc 138 drivers/crypto/inside-secure/safexcel_ring.c (struct safexcel_token *)cdesc->control_data.token; cdesc 146 drivers/crypto/inside-secure/safexcel_ring.c cdesc->control_data.packet_length = full_data_len ?: 1; cdesc 147 drivers/crypto/inside-secure/safexcel_ring.c cdesc->control_data.options = EIP197_OPTION_MAGIC_VALUE | cdesc 150 drivers/crypto/inside-secure/safexcel_ring.c cdesc->control_data.context_lo = cdesc 152 drivers/crypto/inside-secure/safexcel_ring.c cdesc->control_data.context_hi = upper_32_bits(context); cdesc 156 drivers/crypto/inside-secure/safexcel_ring.c cdesc->control_data.options |= EIP197_OPTION_RC_AUTO; cdesc 159 drivers/crypto/inside-secure/safexcel_ring.c cdesc->control_data.refresh = 2; cdesc 165 drivers/crypto/inside-secure/safexcel_ring.c return cdesc; cdesc 172 drivers/net/ethernet/altera/altera_sgdma.c struct sgdma_descrip __iomem *cdesc = &descbase[0]; cdesc 179 drivers/net/ethernet/altera/altera_sgdma.c sgdma_setup_descrip(cdesc, /* current descriptor */ cdesc 189 drivers/net/ethernet/altera/altera_sgdma.c sgdma_async_write(priv, cdesc); cdesc 341 drivers/net/ethernet/altera/altera_sgdma.c struct sgdma_descrip __iomem *cdesc = &descbase[0]; cdesc 352 drivers/net/ethernet/altera/altera_sgdma.c sgdma_setup_descrip(cdesc, /* current descriptor */ cdesc 367 drivers/net/ethernet/altera/altera_sgdma.c csrwr32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)), cdesc 38 drivers/net/ethernet/amazon/ena/ena_eth_com.c struct ena_eth_io_rx_cdesc_base *cdesc; cdesc 45 drivers/net/ethernet/amazon/ena/ena_eth_com.c cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr cdesc 48 drivers/net/ethernet/amazon/ena/ena_eth_com.c desc_phase = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> cdesc 59 drivers/net/ethernet/amazon/ena/ena_eth_com.c return cdesc; cdesc 254 drivers/net/ethernet/amazon/ena/ena_eth_com.c struct ena_eth_io_rx_cdesc_base *cdesc; cdesc 259 drivers/net/ethernet/amazon/ena/ena_eth_com.c cdesc = ena_com_get_next_rx_cdesc(io_cq); cdesc 260 drivers/net/ethernet/amazon/ena/ena_eth_com.c if (!cdesc) cdesc 265 drivers/net/ethernet/amazon/ena/ena_eth_com.c last = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> cdesc 338 drivers/net/ethernet/amazon/ena/ena_eth_com.c struct ena_eth_io_rx_cdesc_base *cdesc) cdesc 340 drivers/net/ethernet/amazon/ena/ena_eth_com.c ena_rx_ctx->l3_proto = cdesc->status & cdesc 343 drivers/net/ethernet/amazon/ena/ena_eth_com.c (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> cdesc 346 drivers/net/ethernet/amazon/ena/ena_eth_com.c !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> cdesc 349 drivers/net/ethernet/amazon/ena/ena_eth_com.c !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> cdesc 352 drivers/net/ethernet/amazon/ena/ena_eth_com.c !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> cdesc 354 drivers/net/ethernet/amazon/ena/ena_eth_com.c ena_rx_ctx->hash = cdesc->hash; cdesc 356 drivers/net/ethernet/amazon/ena/ena_eth_com.c (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> cdesc 362 drivers/net/ethernet/amazon/ena/ena_eth_com.c ena_rx_ctx->hash, ena_rx_ctx->frag, cdesc->status); cdesc 519 drivers/net/ethernet/amazon/ena/ena_eth_com.c struct ena_eth_io_rx_cdesc_base *cdesc = NULL; cdesc 542 drivers/net/ethernet/amazon/ena/ena_eth_com.c cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i); cdesc 544 drivers/net/ethernet/amazon/ena/ena_eth_com.c ena_buf->len = cdesc->length; cdesc 545 drivers/net/ethernet/amazon/ena/ena_eth_com.c ena_buf->req_id = cdesc->req_id; cdesc 556 drivers/net/ethernet/amazon/ena/ena_eth_com.c ena_com_rx_set_flags(ena_rx_ctx, cdesc); cdesc 597 drivers/net/ethernet/amazon/ena/ena_eth_com.c struct ena_eth_io_rx_cdesc_base *cdesc; cdesc 599 drivers/net/ethernet/amazon/ena/ena_eth_com.c cdesc = ena_com_get_next_rx_cdesc(io_cq); cdesc 600 drivers/net/ethernet/amazon/ena/ena_eth_com.c if (cdesc) cdesc 246 drivers/net/ethernet/amazon/ena/ena_eth_com.h struct ena_eth_io_tx_cdesc *cdesc; cdesc 252 drivers/net/ethernet/amazon/ena/ena_eth_com.h cdesc = (struct ena_eth_io_tx_cdesc *) cdesc 260 drivers/net/ethernet/amazon/ena/ena_eth_com.h cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; cdesc 266 drivers/net/ethernet/amazon/ena/ena_eth_com.h *req_id = READ_ONCE(cdesc->req_id); cdesc 268 drivers/net/ethernet/amazon/ena/ena_eth_com.h pr_err("Invalid req id %d\n", cdesc->req_id); cdesc 2167 drivers/net/ethernet/intel/ice/ice_txrx.c struct ice_tx_ctx_desc *cdesc; cdesc 2171 drivers/net/ethernet/intel/ice/ice_txrx.c cdesc = ICE_TX_CTX_DESC(tx_ring, i); cdesc 2176 drivers/net/ethernet/intel/ice/ice_txrx.c cdesc->tunneling_params = cpu_to_le32(offload.cd_tunnel_params); cdesc 2177 drivers/net/ethernet/intel/ice/ice_txrx.c cdesc->l2tag2 = cpu_to_le16(offload.cd_l2tag2); cdesc 2178 drivers/net/ethernet/intel/ice/ice_txrx.c cdesc->rsvd = cpu_to_le16(0); cdesc 2179 drivers/net/ethernet/intel/ice/ice_txrx.c cdesc->qw1 = cpu_to_le64(offload.cd_qw1); cdesc 189 drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2.c const struct mlxfw_mfa2_tlv_component_descriptor *cdesc; cdesc 211 drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2.c cdesc = mlxfw_mfa2_tlv_component_descriptor_get(mfa2_file, tlv); cdesc 212 drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2.c if (!cdesc) { cdesc 217 drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2.c pr_debug(" -- Component type %d\n", be16_to_cpu(cdesc->identifier)); cdesc 219 drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2.c ((u64) be32_to_cpu(cdesc->cb_offset_h) << 32) cdesc 220 drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2.c | be32_to_cpu(cdesc->cb_offset_l), be32_to_cpu(cdesc->size)); cdesc 60 drivers/usb/core/of.c struct usb_config_descriptor *cdesc; cdesc 69 drivers/usb/core/of.c cdesc = &udev->config->desc; cdesc 70 drivers/usb/core/of.c if (cdesc->bNumInterfaces == 1)