cdclk_state 57 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 59 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 133333; cdclk_state 63 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 65 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 200000; cdclk_state 69 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 71 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 266667; cdclk_state 75 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 77 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 333333; cdclk_state 81 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 83 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 400000; cdclk_state 87 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 89 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 450000; cdclk_state 93 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 104 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 133333; cdclk_state 118 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 200000; cdclk_state 121 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 250000; cdclk_state 124 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 133333; cdclk_state 129 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 266667; cdclk_state 135 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 143 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 133333; cdclk_state 149 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 333333; cdclk_state 153 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 190000; cdclk_state 159 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 167 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 133333; cdclk_state 173 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 320000; cdclk_state 177 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 200000; cdclk_state 252 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 263 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); cdclk_state 272 drivers/gpu/drm/i915/display/intel_cdclk.c switch (cdclk_state->vco) { cdclk_state 289 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, cdclk_state 295 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco, tmp); cdclk_state 296 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 190476; cdclk_state 300 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 309 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 266667; cdclk_state 312 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 333333; cdclk_state 315 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 444444; cdclk_state 318 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 200000; cdclk_state 324 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 133333; cdclk_state 327 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 166667; cdclk_state 333 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 343 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); cdclk_state 352 drivers/gpu/drm/i915/display/intel_cdclk.c switch (cdclk_state->vco) { cdclk_state 366 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, cdclk_state 372 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco, tmp); cdclk_state 373 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 200000; cdclk_state 377 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 383 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = intel_hpll_vco(dev_priv); cdclk_state 389 drivers/gpu/drm/i915/display/intel_cdclk.c switch (cdclk_state->vco) { cdclk_state 393 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; cdclk_state 396 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; cdclk_state 400 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco, tmp); cdclk_state 401 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 222222; cdclk_state 407 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 413 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 800000; cdclk_state 415 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 450000; cdclk_state 417 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 450000; cdclk_state 419 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 337500; cdclk_state 421 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 540000; cdclk_state 464 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 471 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = vlv_get_hpll_vco(dev_priv); cdclk_state 472 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", cdclk_state 474 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco); cdclk_state 482 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> cdclk_state 485 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> cdclk_state 526 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 529 drivers/gpu/drm/i915/display/intel_cdclk.c int cdclk = cdclk_state->cdclk; cdclk_state 530 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val, cmd = cdclk_state->voltage_level; cdclk_state 613 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 616 drivers/gpu/drm/i915/display/intel_cdclk.c int cdclk = cdclk_state->cdclk; cdclk_state 617 drivers/gpu/drm/i915/display/intel_cdclk.c u32 val, cmd = cdclk_state->voltage_level; cdclk_state 687 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 693 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 800000; cdclk_state 695 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 450000; cdclk_state 697 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 450000; cdclk_state 699 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 540000; cdclk_state 701 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 337500; cdclk_state 703 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 675000; cdclk_state 709 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = cdclk_state 710 drivers/gpu/drm/i915/display/intel_cdclk.c bdw_calc_voltage_level(cdclk_state->cdclk); cdclk_state 714 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 717 drivers/gpu/drm/i915/display/intel_cdclk.c int cdclk = cdclk_state->cdclk; cdclk_state 780 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level); cdclk_state 823 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 827 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref = 24000; cdclk_state 828 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; cdclk_state 850 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 8100000; cdclk_state 854 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 8640000; cdclk_state 863 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 867 drivers/gpu/drm/i915/display/intel_cdclk.c skl_dpll0_update(dev_priv, cdclk_state); cdclk_state 869 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; cdclk_state 871 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 0) cdclk_state 876 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 8640000) { cdclk_state 879 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 432000; cdclk_state 882 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 308571; cdclk_state 885 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 540000; cdclk_state 888 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 617143; cdclk_state 897 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 450000; cdclk_state 900 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 337500; cdclk_state 903 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 540000; cdclk_state 906 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = 675000; cdclk_state 919 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = cdclk_state 920 drivers/gpu/drm/i915/display/intel_cdclk.c skl_calc_voltage_level(cdclk_state->cdclk); cdclk_state 991 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 994 drivers/gpu/drm/i915/display/intel_cdclk.c int cdclk = cdclk_state->cdclk; cdclk_state 995 drivers/gpu/drm/i915/display/intel_cdclk.c int vco = cdclk_state->vco; cdclk_state 1077 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level); cdclk_state 1126 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state; cdclk_state 1142 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state = dev_priv->cdclk.hw; cdclk_state 1144 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = dev_priv->skl_preferred_vco_freq; cdclk_state 1145 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state.vco == 0) cdclk_state 1146 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 8100000; cdclk_state 1147 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); cdclk_state 1148 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); cdclk_state 1150 drivers/gpu/drm/i915/display/intel_cdclk.c skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); cdclk_state 1155 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; cdclk_state 1157 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = cdclk_state.bypass; cdclk_state 1158 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; cdclk_state 1159 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); cdclk_state 1161 drivers/gpu/drm/i915/display/intel_cdclk.c skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); cdclk_state 1240 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 1244 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref = 19200; cdclk_state 1245 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; cdclk_state 1255 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; cdclk_state 1259 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 1264 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_de_pll_update(dev_priv, cdclk_state); cdclk_state 1266 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; cdclk_state 1268 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 0) cdclk_state 1292 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); cdclk_state 1299 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = cdclk_state 1300 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_calc_voltage_level(cdclk_state->cdclk); cdclk_state 1336 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 1339 drivers/gpu/drm/i915/display/intel_cdclk.c int cdclk = cdclk_state->cdclk; cdclk_state 1340 drivers/gpu/drm/i915/display/intel_cdclk.c int vco = cdclk_state->vco; cdclk_state 1410 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level, 150, 2); cdclk_state 1470 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state; cdclk_state 1478 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state = dev_priv->cdclk.hw; cdclk_state 1486 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = glk_calc_cdclk(0); cdclk_state 1487 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); cdclk_state 1489 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = bxt_calc_cdclk(0); cdclk_state 1490 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); cdclk_state 1492 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); cdclk_state 1494 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); cdclk_state 1499 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; cdclk_state 1501 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = cdclk_state.bypass; cdclk_state 1502 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; cdclk_state 1503 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); cdclk_state 1505 drivers/gpu/drm/i915/display/intel_cdclk.c bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); cdclk_state 1529 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 1534 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref = 24000; cdclk_state 1536 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref = 19200; cdclk_state 1538 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; cdclk_state 1547 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref; cdclk_state 1551 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 1556 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_cdclk_pll_update(dev_priv, cdclk_state); cdclk_state 1558 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; cdclk_state 1560 drivers/gpu/drm/i915/display/intel_cdclk.c if (cdclk_state->vco == 0) cdclk_state 1577 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); cdclk_state 1584 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = cdclk_state 1585 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_calc_voltage_level(cdclk_state->cdclk); cdclk_state 1622 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 1625 drivers/gpu/drm/i915/display/intel_cdclk.c int cdclk = cdclk_state->cdclk; cdclk_state 1626 drivers/gpu/drm/i915/display/intel_cdclk.c int vco = cdclk_state->vco; cdclk_state 1673 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level); cdclk_state 1681 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; cdclk_state 1817 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 1820 drivers/gpu/drm/i915/display/intel_cdclk.c unsigned int cdclk = cdclk_state->cdclk; cdclk_state 1821 drivers/gpu/drm/i915/display/intel_cdclk.c unsigned int vco = cdclk_state->vco; cdclk_state 1850 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level); cdclk_state 1858 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; cdclk_state 1881 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state *cdclk_state) cdclk_state 1885 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->bypass = 50000; cdclk_state 1893 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref = 24000; cdclk_state 1896 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref = 19200; cdclk_state 1899 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref = 38400; cdclk_state 1910 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = 0; cdclk_state 1911 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_state->bypass; cdclk_state 1915 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; cdclk_state 1920 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->cdclk = cdclk_state->vco / 2; cdclk_state 1927 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level = cdclk_state 1928 drivers/gpu/drm/i915/display/intel_cdclk.c icl_calc_voltage_level(dev_priv, cdclk_state->cdclk); cdclk_state 1971 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; cdclk_state 1973 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = cdclk_state.bypass; cdclk_state 1974 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; cdclk_state 1975 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv, cdclk_state 1976 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk); cdclk_state 1978 drivers/gpu/drm/i915/display/intel_cdclk.c icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); cdclk_state 1983 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state; cdclk_state 1991 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state = dev_priv->cdclk.hw; cdclk_state 1993 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = cnl_calc_cdclk(0); cdclk_state 1994 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); cdclk_state 1995 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); cdclk_state 1997 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); cdclk_state 2002 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; cdclk_state 2004 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.cdclk = cdclk_state.bypass; cdclk_state 2005 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.vco = 0; cdclk_state 2006 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); cdclk_state 2008 drivers/gpu/drm/i915/display/intel_cdclk.c cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); cdclk_state 2124 drivers/gpu/drm/i915/display/intel_cdclk.c void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, cdclk_state 2128 drivers/gpu/drm/i915/display/intel_cdclk.c context, cdclk_state->cdclk, cdclk_state->vco, cdclk_state 2129 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->ref, cdclk_state->bypass, cdclk_state 2130 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_state->voltage_level); cdclk_state 2143 drivers/gpu/drm/i915/display/intel_cdclk.c const struct intel_cdclk_state *cdclk_state, cdclk_state 2146 drivers/gpu/drm/i915/display/intel_cdclk.c if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) cdclk_state 2152 drivers/gpu/drm/i915/display/intel_cdclk.c intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); cdclk_state 2154 drivers/gpu/drm/i915/display/intel_cdclk.c dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe); cdclk_state 2156 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), cdclk_state 2159 drivers/gpu/drm/i915/display/intel_cdclk.c intel_dump_cdclk_state(cdclk_state, "[sw state]"); cdclk_state 43 drivers/gpu/drm/i915/display/intel_cdclk.h void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, cdclk_state 968 drivers/gpu/drm/i915/display/intel_display_power.c struct intel_cdclk_state cdclk_state = {}; cdclk_state 972 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->display.get_cdclk(dev_priv, &cdclk_state); cdclk_state 974 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); cdclk_state 258 drivers/gpu/drm/i915/i915_drv.h struct intel_cdclk_state *cdclk_state); cdclk_state 260 drivers/gpu/drm/i915/i915_drv.h const struct intel_cdclk_state *cdclk_state,